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PCI-6035E
National Instruments PCI-6035E Programmer's Manual
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DAQ
PCI E Series Register-Level
Programmer Manual
Multifunction I/O Boards for PCI Bus Computers
PCI E Series RLPM
November 1998 Edition
Part Number 3410
79B-01
2
Table of Contents
Table of Contents
4
Default Chapter
9
About this Manual
9
Conventions Used in this Manual
10
Organization of this Manual
10
Customer Communication
11
Related Documentation
11
Chapter 1 General Description
12
General Characteristics
12
Chapter 2 Theory of Operation
14
Figure 2-1. PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-6071E Block Diagram
14
Functional Overview
14
Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram
15
Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram
16
Figure 2-4. PCI-6032E and PCI-6033E Block Diagram
17
Figure 2-5. PCI-MIO-16XE-50 Block Diagram
18
PCI Interface Circuitry
19
Analog Input and Timing Circuitry
20
Figure 2-6. PCI Bus Interface Circuitry Block Diagram
20
Analog Input Circuitry
21
Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram
21
Table 2-1. PGIA Gain Set Verses Board
22
Data Acquisition Timing Circuitry
24
Single-Read Timing
24
Data Acquisition Sequence Timing
25
Figure 2-8. ADC Timing
25
Figure 2-9. Timing of Scan in Example 1
27
Figure 2-10. Multirate Scanning of Two Channels
28
Figure 2-11. Multirate Scanning of Two Channels with 1:X Sampling Rate
28
Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate
29
Figure 2-13. Multirate Scanning of Three Channels with 4:2:1 Sampling Rate
29
Figure 2-14. Multirate Scanning Without Ghost
30
Figure 2-16. Successive Scans Using Ghost
30
Posttrigger and Pretrigger Acquisition
31
Table 2-2. Analog Input Configuration Memory
31
Analog Triggering
32
Analog Output and Timing Circuitry
33
Figure 2-17. Analog Output Circuitry Block Diagram
33
Analog Output Circuitry
34
Analog Output Timing Circuitry
35
Single-Point Output
35
Waveform Generation
36
Digital I/O Circuitry
37
Figure 2-18. DAQ-STC Counter Diagram
37
Timing I/O Circuitry
37
RTSI Bus Interface Circuitry
38
Figure 2-19. RTSI Bus Interface Circuitry Block Diagram
39
Chapter 3 Register Map and Descriptions
40
Register Map
40
Table 3-1. PCI E Series Register Map
41
Register Sizes
42
Register Descriptions
42
Misc Register Group
42
Table 3-2. PCI E Series Windowed Register Map
42
Serial Command Register
43
Misc Command Register
44
Status Register
45
Analog Input Register Group
46
ADC FIFO Data Register
47
Configuration Memory Low Register
48
Table 3-3. PGIA Gain Selection
49
Configuration Memory High Register
50
Table 3-4. Calibration Channel Assignments
51
Table 3-5. Differential Channel Assignments
52
Table 3-6. Nonreferenced Single-Ended Channel Assignments
52
Table 3-7. Referenced Single-Ended Channel Assignments
53
Analog Output Register Group
54
Table 3-8. Auxiliary Channel Assignments
54
Table 3-9. Channel Assignments
54
AO Configuration Register
55
DAC FIFO Data Register
57
DAC0 Direct Data Register
58
DAC1 Direct Data Register
59
DMA Control Register Group
60
AI AO Select Register
61
G0 G1 Select Register
62
DAQ-STC Register Group
63
FIFO Strobe Register Group
63
ADC FIFO Clear Register
63
Configuration Memory Clear Register
63
DAC FIFO Clear Register
63
Chapter 4 Programming
64
Pcl Local Bus
64
PCI Initialization for the IBM Compatible System
65
Re-Mapping the PCI E Series Board
66
PCI Initialization for the Macintosh
67
Programming Examples
68
Windowing Registers
68
Digital I/O
70
Example 1
70
Example 2
70
Analog Input
71
Example 1
72
Example 2
75
Example 3
77
Example Program
78
Default Chapter
80
Example 4
80
Programming the MITE for Different DMA Transfers
83
Call the Function Number_Of_Scans to Load the Number of Scans
84
AI Configuration Start = 1; Ai_Sc_Load_A_Registers (24 Bits) Number of Posttrigger Scans -1 = 4; Ai_Command_1_Register
84
AI SC Load = 1
84
Joint_Reset_Register
84
Example 5
84
Perform Analog Input Example 1 Step 1
84
Perform Analog Input Example 1 Step 2 for each Channel in the Scan List. Only Channel 0 Has Last Channel Set to
84
Perform Analog Input Example 1 Steps
84
Example 6
86
Example 7
88
Joint_Reset_Register
88
Example 8
90
AI Configuration Start = 0; AI Configuration End = 1; the Function Ai_Scan_Start
90
Perform Analog Input Example 1 Step
90
Example 9
92
The Function Ai_Scan_Start Selects the Scan Start Event
90
AI Configuration Start = 0; AI Configuration End
90
AI Configuration Start = 1
90
Ai_Command_1_Register
90
Joint_Reset_Register
90
Analog Output
94
Example 1
95
Example 2
97
Example 2
102
Example 3
102
Example 3
104
Example 4
104
Example 5
106
Example Program
106
General-Purpose Counter/Timer
108
Example 1
108
Example 2
110
Example 3
112
Analog Triggering
115
RTSI Trigger Lines Programming Considerations
115
Figure 4-1. Analog Trigger Structure
117
Interrupt Programming
119
Interrupt Sharing
119
DMA Programming
120
Figure 4-2. DMA Structure
120
The Link Chaining Mode for DMA Transfer
121
Figure 4-3. DMA Link Chaining Mode Structure
122
Chapter 5 Calibration
123
About the EEPROM
123
Figure 5-1. EEPROM Read Timing
124
Table 5-1. PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6071E EEPROM Map
125
Table 5-2. PCI-MIO-16XE-50 EEPROM Map
127
Table 5-3. PCI-MIO-16XE-10, PCI-6031E, PCI-6032E and PCI-6033E EEPROM Map
129
Table 5-4. PCI-6023E EEPROM Map
131
Table 5-5. PCI-6024E and PCI-6025E EEPROM Map
132
Table 5-6. PCI-6052E EEPROM Map
134
Calibration Dacs
136
Figure 5-2. Calibration AC Write Timing
138
NI-DAQ Calibration Function
139
Appendix A Customer Communication
140
Glossary
145
Index
152
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National Instruments PCI-6035E Specifications
General
Brand
National Instruments
Model
PCI-6035E
Category
Computer Hardware
Language
English
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