PIN
SIGNAL NAME TYPE
(1)
PULL
(2)
GPIO
(3)
DESCRIPTION
NO.
External Memory Interface (EMIF) Address and Control
EM_A[0] 91 O - N
EM_A[1] 89 O - N
EM_A[2] 88 O - N
EM_A[3] 86 O - N
EM_A[4] 84 O - N
EM_A[5] 83 O - N
EMIF Address Bus
EM_A[6] 80 O - N
EM_A[7] 79 O - N
EM_A[8] 76 O - N
EM_A[9] 75 O - N
EM_A[10] 93 O - N
EM_A[11] 74 O - N
EM_BA[0] 96 O - N
SDRAM Bank Address and Asynchronous Memory
Low-Order Address
EM_BA[1] 94 O - N
EM_CS[0] 97 O - N SDRAM Chip Select
EM_CS[2] 100 O - N Asynchronous Memory Chip Select
EM_CAS 37 O - N SDRAM Column Address Strobe
EM_RAS 98 O - N SDRAM Row Address Strobe
EM_WE 38 O - N SDRAM Write Enable
EM_CKE 71 O - N SDRAM Clock Enable
EM_CLK 70 O - N SDRAM Clock
EM_WE
_DQM[0] 39 O - N Write Enable or Byte Enable for EM_D[7:0]
EM_WE
_DQM[1] 67 O - N Write Enable or Byte Enable for EM_D[15:8]
EM_OE 104 O - N SDRAM Output Enable
EM_RW 102 O - N Asynchronous Memory Read/not Write
(1) TYPE column refers to pin direction in functional mode. If a pin has more than one function with different directions, the functions are
separated with a slash (/).
(2) PULL column:
IPD = Internal Pulldown resistor
IPU = Internal Pullup resistor
(3) If the GPIO column is 'Y', then in GPIO mode, the pin is configurable as an IO unless otherwise
marked.
TX-SR604/604E/8460
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -41
Q201 : TMS320DA707 (32 bit Floating-Point Digital Signal Processor)
TERMINAL DESCRIPTION (1/4)
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