Table 14. Ethernet related jumpers
Jumper Description
JP5
50M RMII reference clock is generated by an external crystal X3 when JP5 is set as shown below: (Default setting)
50M RMII reference clock is generated by MCO at PA8 when JP5 is set as shown below:
6.16 Memories
An 8M x 32-bit SDRAM is connected to the SDRAM bank1 of the FMC interface of the STM32H7x7XI
microcontroller.
A 1Mx16-bit SRAM is connected to the NOR/PSRAM2 bank1 of the FMC interface and both 8-bit and 16-bit
accesses are allowed by BLN0 and BLN1, connected to BLE and BHE of SRAM respectively.
A 128-Mbit NOR Flash is connected to the NOR/PSRAM1 bank1 of the FMC interface. The 16-bit operation mode
is selected by pull-up resistor connected to the BYTE pin of NOR Flash memory. The write protection can be
enabled or disabled, depending on how the jumper JP13 is set, as showed in Table 15. NOR Flash related
jumpers.
Table 15. NOR Flash related jumpers
Jumper Description
JP13
Write protection is enabled when JP13 is ON while write protection is disabled when JP13 is OFF.
Default Setting: OFF
All signals for memory are also connected on memory connectors CN11 and CN12 for memory daughterboards.
Limitations can happen when using other peripherals:
1. FMC addressing limitation depending on number of trace data bus used (A18 max for 4 bit ETM to A21 max
for 1 bit ETM)
2. FMC addresses limited to A18 when SAI used
3. FMC addresses limited to A22 when PDM is used
In such cases, serial resistors R236 (A19), R231 (A20), R217 (A21) and R230 (A22) should be removed. Thus
memory addresses A19 to A22 are not connected to FMC and they are pulled down on the board. Memories can
be addressed within a limited address range.
By default, all these serial resistors are soldered on the board. If A19 is required, it is necessary to configure
(SAI_SDB) ADCDAT1 pin of audio codec WM8994ECS/R (U22) by software to be tri-state.
6.17
Twin Quad-SPI NOR Flash memory
The Quad-SPI Flash memory is implemented on the STM32H7x7XI microcontroller of the Evaluation board either
as 1 Twin Quad-SPI NOR Flash memory (1-Gbit (2*512 Mb)) memory or as two Quad-SPI NOR Flash (512 Mb)
memories.
The two dies in the Twin Quad-SPI Flash memory share the same clock and chip select signals of the
STM32H7x7XI microcontroller.
6.18
Analog input
The two-pin header CN5 and 10 KΩ potentiometer RV1 is connected to PA0_C of STM32H7x7XI as analog input.
A low-pass filter can be implemented by replacing R11 and C7 with the right value of resistor and capacitor as
requested by the end-user application.
UM2525
Memories
UM2525 - Rev 3
page 19/69
To Next Page
Loading...
Need help?
General
