Table 2-1. Dual TPS6594-Q1 Orderable Part Numbers for Independent MCU and Main PDN System
PDN USE CASE PDN Orderable Part
Number
TI_NVM_ID
(TI_NVM_REV)
Orderable Part
Number
TI_NVM_ID
(TI_NVM_REV)
Error Signal
Monitoring
• Up to 9 A
(1)
on the Primary PMIC 3-
phase CPU rail
• Up to 12 A
(1)
on the Secondary PMIC
4-phase CORE rail
• Up to 3.4 A
(1)
on the SDRAM, with
support for LPDDR4
• Supports Processor 2 GHz maximum
clock with high-speed SERDES
operations
• Supports 32 Gb of LPDDR4 SDRAM
with 4266MTs data rate
• Supports Functional Safety up to
ASIL-D level with MCU Safety Island
• Supports MCU-only and Retention
(2)
low power modes
• Supports I/O level of 3.3 V or 1.8 V
• Supports optional end product
features:
– Compliant high-speed SD Card
memory
– Compliant USB 2.0 Interface
– On-board Efuse programming of
high security processors
0C
(3)
TPS65941213
RWERQ1
0x13 (0x04) TPS65941111
RWERQ1
0x11 (0x03) Dedicated MCU
and SOC
0B TPS65941212
RWERQ1
0x12 (0x03) TPS65941111
RWERQ1
0x11 (0x03) Combined MCU
and SOC
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC
output rail.
(2) Retention, either GPIO or RAM, is configured by the processor.
(3) PDN-0C is recommended for all new designs.
www.ti.com Device Versions
SLVUC99 – JANUARY 2022
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