At the end of the TO_ACTIVE sequence the 'FORCE_EN_DRV_LOW' bit is cleared.
Note
After the TO_ACTIVE sequence the MCU is responsible for managing the EN_DRV.
6.3.9 TO_RETENTION
The C and D triggers, defined by the NSLEEPx bits or pins, trigger the TO_RETENTION sequence. This
sequence disables all power rails and GPIOs that are not supplying the retention rails, as described in Figure
3-1. The sequence can be modified using the I2C_7 bit found in register FSM_I2C_TRIGGERS. These bits need
to be set by I
2
C in both PMICs before a trigger for the retention state occurs. If the I2C_7 bit is set high in
both PMICs, they enter the DDR retention state as shown in Figure 6-13. LDO1 (VDD1) is not disabled and the
GPIO3 of the TPS6591111 (EN_VDDR) is also unchanged. If I2C_7 is set low, these components associated
with DDR do not remain active, as shown in Figure 6-12.
Note
The I2C_7 bits need to be set or cleared by I
2
C in both PMICs before a trigger to the retention state
occurs. The I2C_7 trigger is not self-clearing and must be maintained during operation.
In addition to the I2C_7, the processor must also configure the H_DDR_RET_1V1 signal on GPIO4 of the
TPS65941111 device. This signal is included in the Section 3.2 but is not part of the power sequence.
The following PMIC PFSM instructions are executed automatically in the beginning of the power sequence to
configure the PMICs:
// TPS65941213
// Set LPM_EN, Clear NRSTOUT_SOC and NRSTOUT
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xF8
// Set SPMI_LP_EN and FORCE_EN_DRV_LOW
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x18 MASK=0xE7
//TPS65941111
// Set SPMI_LP_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUC99 – JANUARY 2022
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Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
47
Copyright © 2022 Texas Instruments Incorporated
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