Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 12
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 1: Introduction
The remaining blocks are common to all designs. See Chapter 2, Targeted Reference Design
Details for more details.
The reference design targets the ZCU106 evaluation board. The board has an onboard
HDMI transmitter and receiver connector, SDI transmitter and receiver connector, and a
DisplayPort connector interface. The evaluation board provides the HDMI reference clock,
data recovery unit (DRU) clock, and the reference clock for the design. The PS_REF_CLK is
sourced from another dedicated clock generator present on the evaluation board.
Figure 1-4 shows the block diagram of the TRD along with the board components.
Key Features
Target platforms and extensions:
• ZCU106 evaluation board (see ZCU106 Evaluation Board User Guide (UG1244)) [Ref 2]
• Optional: Leopard Imaging LI-IMX274MIPI-FMC image sensor daughter card [Ref 3]
• SDI Receiver - Blackmagic Design Teranex Mini HDMI to 12G converter
• SDI Transmitter - Blackmagic Design Teranex Mini 12G to HDMI converter
X-Ref Target - Figure 1-4
Figure 1-4: High-Level Block Diagram of ZCU106 Device Architecture
Live video source
(HDMI/TPG/SDI/MIPI)
File/streaming source
PS CLK
(Si5341)
33.33 MHz
PS DDR Memory
Capture
Pipeline
(Audio/Video
Processing
Pipeline
Render
Pipeline
(Audio/Video
Video Sink
(HDMI/SDI/DP)
SFP_SI5328_out
Si5328
156.25 MHz
Audio Sink
(HDMI/SDI/DP/I2S
PL DDR Memory
Live audio source
(HDMI/SDI/I2S)
X19301-041719
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Xilinx Zynq UltraScale+ Specifications

General

Brand	Xilinx
Model	Zynq UltraScale+
Category	Conference System
Language	English