Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 5
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 1
Introduction
About this TRD
This document describes the features and functions of the Zynq® UltraScale+™ MPSoC
Video Codec Unit (VCU) targeted reference design (TRD). The VCU TRD is an embedded
video encoding/decoding application partitioned between the SoC processing system (PS),
VCU, and programmable logic (PL) for optimal performance. The design demonstrates the
capabilities and performance throughput of the VCU embedded macro block available in
Zynq UltraScale+ MPSoC devices.
The TRD serves as a platform to tune the performance parameters of the VCU to arrive at
optimal configurations for encoder and decoder blocks.
The TRD demonstrates the following hard block features in the PS and PL:
• VCU hard block capable of performing up to 4K (3840 x 2160) @60 Hz
• Simultaneous encoding and decoding of single and multiple streams
• PS DisplayPort controller for 4K (3840 x 2160) @ 30 Hz
•PL-based HDMI-TX/SDI-TX for 4K (3840 x2160) @ 60 Hz
• GPU used for rendering a graphical user interface (GUI)
• Extensible platform uses:
°
GStreamer v1.14.4 pipeline architecture to construct a multimedia pipeline [Ref 1]
°
Standard Linux software frameworks
°
OpenMAX™ v1.1.2 based client interface for the VCU
°
Modular and hierarchical architecture (enables partner modules)
°
Configurable IP Subsystems
• System software configuration:
°
Linux symmetric multi-processing (SMP) on the application processing unit (APU)
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Xilinx Zynq UltraScale+ Specifications

General

Brand	Xilinx
Model	Zynq UltraScale+
Category	Conference System
Language	English