Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 24
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 3: APU Software Platform
Media Framework
The main goal of the media framework is to discover the device topology of a video pipeline
and to configure it at run time. To achieve this, pipelines are modeled as an oriented graph
of building blocks called entities connected through pads.
X-Ref Target - Figure 3-2
Figure 3-2: VL42 Driver Stack
vcu_qt/vcu_gst_app
vcu_gst_lib
libv4lsubdev
libv4I2 libmediactl
User Space
Kernel Space
/dev/v4I-subdev* /dev/video* /dev/media*
DMA Engine
Channel
DMA
V4L2 subdev
XVIPP Driver
TPG
Fmbuf Wr
VPSS
(Scaler Only)
Fmbuf Wr
TPG Capture Pipeline
HDMI Rx Capture Pipeline
CSK-2 Rx Capture Pipeline
SDI Rx Capture Pipeline
SDI Rx
Fmbuf Wr
IMX274
MIPI
CSI-2
RX
Demosaic Gamma
VPSS
CSC
VPSS
Scaler
Fmbuf Wr
VTC
HDMI Rx
X19930-120118
HW
VPSS
(Scaler Only)
vcu_apm_lib
vcu_video_lib
SCD
SCD Pipeline
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Xilinx Zynq UltraScale+ Specifications

General

Brand	Xilinx
Model	Zynq UltraScale+
Category	Conference System
Language	English