— 14 —
Pin No. Name In/Out Description
57 MS2 Out Not used
58 OEO Out Output enable for ROM
59 BZ1 Out Buzzer signal
60 OTP In Connected to GND
61 BZ2 Out Buzzer signal
62 SWO Out Main switch control signal
63 VH4(VCC) In 9V input
64 TXO Out Transmission data output terminal
Pin No. Name In/Out Description
1 VSS1 In GND terminal
2 OSO Out Clock out
3 OSI In Clock in
4 VL1 In 6V input
5~10 A0~3,A14,15 In Address input
11 FE In Chip select signal from CPU
12 CS1 In Chip select signal from CPU
13 CS2 In Chip select signal from CPU
14 CS3 In Chip select signal from CPU
15 OEI In Output enable signal from CPU
16 VSS(GND) In GND terminal
17 VH1(VCC) In 9V input
18 TXI In Transmission data input from CPU
19 WEI In Write enable signal from CPU
20 GC In GC signal from CPU
21 IO0 In/Out Data bus lin
22 DT In DT signal input
23 IO1 In/Out Data bus lin
24 VIN In Power ON signal from CPU (V2ON)
25 IO2 In/Out Data bus lin
26 KON Out Switch control signal
27 IO3 In/Out Data bus lin
28 VOB Out Inverted signal for VIN
29 IO4 In/Out Data bus lin
30 INT Out Interrupt signal
31 VH2(VCC) In 9V input
32 VL2(VLL) In 6V input
33 VSS(GND) In GND terminal
34 BBC Out Not used
35 PDN In Power down detection input
36 IO5 In/Out Data bus lin
37 LRAM Out Connected to 9V
38 CM32 Out Connected to GND
39 IO6 In/Out Data bus lin
40 RA16 Out Inverted signal for VIN
41 IO7 In/Out Data bus lin
42 RA17 Out Address bus output
43 RA18 Out Address bus output
44 MS3 Out Not used
45 RA19 Out Not used
Gate array pin descriptions (SSC2571F0B): Used in SF-8900