Cisco UCS C480 M5 Guide

Cisco UCS C480 M5 Memory Guide
DIMM Memory Mirroring
11
Normal CPU/Memory Configuration (no memory mirroring)
There are two CPU modules, one in each CPU bay. The lower CPU module occupies Bay 1 and the upper CPU
module occupies Bay 2. CPU 1 and CPU2 are in Bay 1; CPU 3 and 4 are in Bay 2.
Select from 4, 6, 8, or 12 DIMMs per CPU (DIMMs for
all four CPUs must be configured identically). The
DIMMs will be placed by the factory as shown in the following tables.
CPU 1 DIMM Placement in Channels (for identically ranked DIMMs)
4 (A1, B1); (D1, E1)
6 (A1, B1, C1); (D1, E1, F1)
8 (A1, A2, B1, B2); (D1, D2, E1, E2)
12 (A1, A2, B1, B2, C1, C2); (D1, D2, E1, E2, F1, F2)
CPU 2 DIMM Placement in Channels (for identically ranked DIMMs)
4 (G1, H1); (K1, L1)
6 (G1, H1, J1); (K1, L1, M1)
8 (G1, G2, H1, H2); (K1, K2, L1, L2)
12 (G1, G2, H1, H2, J1, J2); (K1, K2, L1, L2, M1, M2)
CPU 3 DIMM Placement in Channels (for identically ranked DIMMs)
4 (A1, B1); (D1, E1)
6 (A1, B1, C1); (D1, E1, F1)
8 (A1, A2, B1, B2); (D1, D2, E1, E2)
12 (A1, A2, B1, B2, C1, C2); (D1, D2, E1, E2, F1, F2)
CPU 4 DIMM Placement in Channels (for identically ranked DIMMs)
4 (G1, H1); (K1, L1)
6 (G1, H1, J1); (K1, L1, M1)
8 (G1, G2, H1, H2); (K1, K2, L1, L2)
12 (G1, G2, H1, H2, J1, J2); (K1, K2, L1, L2, M1, M2)

Cisco UCS C480 M5 Specifications

General

Processor	Up to two Intel Xeon Scalable processors
Management	Cisco Integrated Management Controller (CIMC)
Memory	Up to 6 TB
Drive Bays	Up to 12 x 3.5-inch or 24 x 2.5-inch
Expansion Slots	Up to 8 PCIe 3.0 slots
Power Supply	Up to four 2000W or 1600W power supplies
DIMM Slots	24 DIMM slots