Clevo W240HU Series User Manual

Schematic Diagrams
B - 4 CPU 2/7 (CLK, MISC, JTAG)
B.Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)
H_PRO CH OT#[36]
S
D
G
Q3 6 B
MT D N7 0 02 Z H S6 R
5
3
4
R91 100K_04
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3 MISC
JTAG & BPM
U3 4 B
P Z98827-364B-01F
SM _RC OMP [1]
A5
SM _RC OMP [2]
A4
SM_DR AMR ST#
R8
SM _RC OMP [0]
AK1
BC LK#
A27
BC LK
A28
DPLL _ REF_SSC L K#
A15
DPLL_R EF_SSC LK
A16
CATERR #
AL33
PECI
AN 33
PRO CH OT#
AL32
TH ERM TRIP#
AN 32
SM_DR AMPW RO K
V8
RESET#
AR 33
PR DY #
AP29
PREQ #
AP27
TCK
AR26
TMS
AR27
TR S T #
AP30
TDI
AR28
TDO
AP26
DBR #
AL3 5
BPM # [0]
AT28
BPM # [1]
AR29
BPM # [2]
AR30
BPM # [3]
AT30
BPM # [4]
AP32
BPM # [5]
AR31
BPM # [6]
AT31
BPM # [7]
AR32
PM_SYN C
AM 34
SKTOCC #
AN 34
PRO C_SELECT#
C26
UNCOREPWRGOOD
AP33
C2 2
0.047u_10V_X7R _04
R59 0_04
S3 c ir cuit:- DR AM P WR GOOD lo gic
1.8VS_PWRG D[15,3 3 ]
PM_DR AM_PW R GD[1 5]
P MSY S_P WRG D_BUF
R73
*200_1%_04
1.5V_CPU
R57
10K_04
R58
*39_04
SUSB[6 ,3 1,3 3 ,3 4 ]
Q10
*MTN7002ZH S3
G
DS
3.3V
11/0 3
S
D
G
Q36A
MT D N7 0 02 ZH S 6 R
2
6
1
R530 10K_04
11/ 04
C515
47p_50V_NPO _04
H_PR OCH OT#
R90 *0_04
R 60 130_1% _04
CAD Note: Capacitor
need to be placed
close to buffer output pin
H_PR OC HO T_ EC[27 ]
Q1 4
MTN 7002ZHS3
G
DS
C
A
A
D20
*B AT54AW G H
1
2
3
PM SYS_PWR GD _BUF
R 414 51_04
R 416 51_04
R 108 51_04
R 415 51_04
R 109 * 51_04
R 95 51_04
3.3VS
1. 0 5 V S _ V T T
XD P _ D B R _RR 407 1K_04
XD P _ T M S
XD P _ T D O _ R
PU/P D fo r JT AG sig na ls
XD P_TR ST#
XD P_PREQ #
XD P _ T D I _ R
XD P _ T C L K
H_ C PUPW R GD _ R
R106
*750_1%_04
R112 *1.5K_1%_04
Proc es sor Pullups/ Pu ll downs
TRACE WIDTH 10MIL, LENGTH <500MILS
3.3VS
BUF_CPU_RST#
DDR3 Compensation Signals
SM_R CO MP_2
SM_R CO MP_1
SM_R CO MP_0
C9 6
*68p_50V_NPO _04
VDD PW R GO OD_R
XDP_TRST#
XDP_TCLK
PLT_R ST#[17,23]
XDP_TMS
XDP_TDI_R
CPUDRAMRST#
H_ PR OC HO T# _ D
H_ C ATE RR#
Buff er ed reset to CPU
XDP_TDO _R
XDP_PR EQ#
H_THR MTR IP#[1 8 ]
H _S NB_IVB#[18]
R 38 2 2 5 . 5 _1 % _ 04
R 381 200_1%_04
R419 *10mil_04
R 412 10K_04
R 413 140_1%_04
H_PECI[18,27]
PM_SY NC _R
If PROCHOT# is not used, then it must
be terminated with a 68-O +-5% pull-up
resistor to 1.05VS_VTT .
Sandy Bridge Processor 2/7
( CLK,MISC,JTAG )
R418 *10mil_04
R410 62_04
1.05VS_VTT
H_PROCHOT#
SM _ RC OMP _2
SM _ RC OMP _0
SM _ RC OMP _1
CLK_DP_N [ 14]
CL K_ EXP _N [1 4]
CL K_ EXP _P [14 ]
H_PM _S YN C[15 ]
CLK_DP_P [14]
H_SN B_IVB#
1.5V[6,8 ,9,10 ,20,26 ,28 ,31,33 ]
1.5V _C PU[6,3 1 ]
1.05VS_VTT[2 ,5 ,1 8,1 9 ,2 0 ,34 ,3 6 ]
3.3V[ 2,8,11,13,14,15,17,18, 19,20,22,23,26,28,30,31,33,34,35]
H_CPUPWRGD[1 8]
Q8
MTN 7002ZHS3
G
DS
R46
4.99K_1%_04
C PUD RAM RST#
R47 *0_04
1.5V
R45
1K _ 0 4
S3 circuit:- DRAM_RST# to memory
should be high during S3
DRAMRST_CNTRL [8,14]
DDR3_DRAMRST# [9,10]
R48 1K_04
10/1
XDP_DB R_R
R411 *10mil_04
XDP_BPM 1_R
XDP_BPM 0_R
XDP_BPM 6_R
XDP_BPM 5_R
XDP_BPM 4_R
XDP_BPM 3_R
XDP_BPM 2_R
XDP_BPM 7_R
H_PEC I_R
R105 75_1%_04
R405 56_1%_04
H_CPUPWRGD_R
R 1 04 43 _ 1 % _ 0 4
10 /2 9
R531
100K_04
C 585 *0.1u_10V_X7R_04
XDP_PR DY#
10/28
1.05VS_VTT
3.3V S[9,10,11,12,13,14,15,16,17,18, 19,20,23,24,25,27,28,29,30,31,36]
R417 *10mil_04
H_THR MTRI P#_R
Sheet 3 of 43
CPU 2/7
(CLK, MISC, JTAG)

Clevo W240HU Series Specifications

General

Brand	Clevo
Model	W240HU Series
Category	Laptop
Language	English