III PERIPHERAL BLOCK: WATCHDOG TIMER
B-III-5-2 EPSON S1C33L03 FUNCTION PART
Resetting the watchdog timer
When using the watchdog timer, prepare a routine to reset the 16-bit programmable timer 0 before an NMI is
generated in a location where it will be periodically processed. Make sure this routine is processed within the
NMI generation interval described above.
The 16-bit programmable timer 0 is reset by writing "1" to PRESET0 (D1) / 16-bit timer 0 control register
(0x48186). At this point, the timer counter is set to 0, and the timer starts counting the NMI generation
interval over again from that point.
If the watchdog timer is not reset within the set interval for any reason, the CPU is made to enter trap
processing by an NMI and starts executing the processing routine indicated by the NMI vector.
The NMI trap vector address is set to 0x0C0001C by default.
The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137).
Operation in Standby Modes
During HALT mode
In HALT mode (basic mode or HALT2 mode), the prescaler and watchdog timer are operating. Consequently,
if HALT mode continues beyond the NMI generation interval, HALT mode is cleared by the NMI.
To disable the watchdog timer in HALT mode, set EWD to "0" before executing the halt instruction or turn
off the 16-bit programmable timer 0.
If the NMI is disabled by EWD, the 16-bit programmable timer 0 continues counting even in HALT mode.
To reenable the NMI after clearing HALT mode, reset the 16-bit programmable timer 0 in advance.
If HALT mode was entered after the 16-bit programmable timer 0 was turned off, reset the timer before
restarting it.
During SLEEP mode
In SLEEP mode, the prescaler is turned off. Therefore, the watchdog timer also stops operating. To prevent
generation of an unwanted NMI after clearing SLEEP mode, reset the 16-bit programmable timer 0 before
executing the slp instruction. In addition, disable generation of the NMI by EWD as necessary.
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