Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 User Manual

V DMA BLOCK: IDMA (Intelligent DMA)
S1C33L03 FUNCTION PART EPSON B-V-3-7
A-1
B-V
IDMA
IDMA invocation request during a DMA transfer
An IDMA invocation request to another channel that is generated during a DMA transfer is kept pending until
the DMA transfer that was being executed at the time is completed. Since an invocation request is not cleared,
new requests will be accepted when the DMA transfer under execution is completed.
An IDMA invocation request to the same channel canot be accepted while the channel is executing a DMA
transfer because the same interrupt factor is used. Therefore, an interval longer than the DMA transfer period
is required when invoking the same channel.
IDMA invocation request when DMA transfer is disabled
An IDMA invocation request generated when IDMAEN is "0" (DMA transfer disabled) is kept pending until
IDMAEN is set to "1". Since an invocation request is not cleared, it is accepted when DMA transfer is
enabled.
Simultaneous generation of a software trigger and a hardware trigger
When a software trigger and the hardware trigger for the same channel are generated simultaneously, the
software trigger starts IDMA transfer. The IDMA transfer by the hardware trigger is not executed since the
interrupt factor is reset when the DMA transfer is completed. However, an operation like this cannot be
recommended.

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Specifications

General

Brand	Epson
Model	CMOS 32-Bit Single Chip Microcomputer S1C33L03
Category	Computer Hardware
Language	English