Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 3-5
3.4 Wired-OR Signal Considerations
The Wired-OR signals of the processor’s host bus require additional consideration. The Wired-OR
signals in an Intel
®
Pentium
®
III Processor with 512KB L2 Cache system are HIT#, HITM#, BNR#,
AERR#, BERR#, and BINIT#. The Wired-OR signals may be driven by multiple bus agents at the same
time, such as both processors asserting the HIT# signal to signify a cache hit on a line they both contain.
With multiple driving agents, these signals are susceptible to being overdriven which results in excessive
overshoot and ringback on these signals.
Terminating the Wired-OR signals at the chipset branch of the T topology will reduce the effect of multiple
driving agents on these signals. Intel recommends that system designers carefully examine the signal
integrity of these signals and optionally implement the circuit shown in Figure 3-3. This recommendation
will work correctly for systems designed with the standard T topology or the terminator-less T topology.
Please note that the incorporation of Wired-OR termination is optional. Intel has not seen any failures on
systems which do not implement the Wired-OR termination recommendations. Therefore, systems which
are already in the latter phases of design may wish to forego implementing these recommendations until
an opportunity presents itself to incorporate them. However, it is the responsibility of the system designer
to ensure that the signal quality of these signals meet the component specifications.
Table 3-7. Trace Lengths for Terminator-less T Topology (ServerWorks Chipset)
Segment Min Length (inches) Max Length (inches)
L0 3.25 3.75
L1 3.25 3.75
L2 1.75 2.5
L3 0.0 1.0
Table 3-8. Component Values for Terminator-less T Topology
Reference Value Tolerance
R1 (on chip) 68Ω 10%
R2 (on chip) 100Ω 15%
R3 68Ω 1%
R4 100Ω 1%
R5 100Ω 10%
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