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Troubleshooting

2-87

Bit patterns

Test 408.3 — Setup for test 408.5 and A/D measurement for test 408.6

Type

Circuit Exercise

Fault message

None

Description

In this phase, DAC A is programmed with 0s, and the output pin 2 is tied to C461. BUFF is ap-

plied to NET1 (R488) through R493. The divided voltage at pin 4 is tied to AC buffer Q418 and

U423 through U428 and Q422. The signal AMP IN is tied to the circuit through U425, U426, to

Q414. This phase sets up the conditions for the next phase. The voltage on C439 that is buffered

by Q409 (SELFTEST OUT) is tied to U414 pin 11. The output of U414 is tied to the A/D buffer

through buffer U403, R434, R462, and U222. The A/D buffer is conﬁgured in X1 gain. This

measurement is saved and used in a comparison in test 408.6.

Drawing reference

Analog Board; 2002-100

Bit patterns

Bit pattern* Register

—U400—

01111101

—U811—

00001101

—U224—

00010111

—U432—

11111111

—U810—

00000011

—U206—

01110000

—U203—

10001110

—U411—

00111011

—U809—

11100111

—U207—

11001111

—U221—

11101001

—U406—

01101100

AD_STB

MUX_STB

R1_STB

R2_STB

*Bits associated with register IC terminals as follows:

QQQQQQQQ

87654321 87654321 87654321 87654321

IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4.