TK-760/762
CIRCUIT
DESCRIPTION
4.
Frequency Synthesizer
Unit
4-1. VCO/PLL
The PLL generates the transmit signal and the first
local oscillator receive signal. The
RF
signal generated
by
05
(TX)
or
02
(RX)
in
the
VCO
unit
is
amplified by
03,
and the resulting signal
is
output to the
TX-RX
unit.
TX
and
RX
05
and
02
are
switched by turning the
source line for
05
and
02
on
and off. This
is
done by
04
and 01 using the control signal
(STR)
generated by
the serial-to-parallel converter
in
the
TX-RX
unit. The
RF
signal passes through
03
of the
VCO
unit and am-
plifier
0209
of the
TX-RX
unit, and
is
input to IC202
(PLL
IC).
The 12.8MHz
PLL
reference signal generated
by the VCXO
(X1)
in
the
TX-RX
unit is also input to
IC202.
Both signals
are
divided according to the division
data from the control unit to produce a 12.5kHz signal.
The phases are compared, and a phase difference sig-
nal
is
output and passes through the charge pump
(in
IC202) and the low-pass filter of the lug lead to produce
the control voltage for
05/02
(VCOl. This voltage
is
applied to
D3
and D4
(TX)
or
D1
and
D2
(RX)
in
the
VCO
unit to keep the
VCO
frequency constant. The other
output from
03
is
amplified by the
RF
amplifier (018),
and output to the transmit or receive unit
via
the
RF
switch (D17).
...----1
(----
RX
8R
I--'-
.......Kf--...-I(----TX
11
-,
I
I
I
0209
PLL
DATA
K
~==--'=====::::::::::J
CK
(CLOCK)
DT (DATA)
'--_.....
EP
(ENABLE)
1 J
I
I
I
I
I
I
__________
J
IC202
PLL
IC
r-----------
Fig. 6
PLL
unit block diagram
4-2.
PLL
unlock
When the
PLL
is
unlocked, the lock detect signal
(LD)
of the
PLL
IC
(lC202)
is
rectified by D212, and con-
verted to a
DC
signal. The
CPU
monitors this signal.
When the PLL
is
unlocked, the
CPU
turns the key out-
put signal off (Iowl, then turns
010,
06,
and
8T
off
to
prevent unnecessary transmission.
8T
Fig.
7
PLL
unlock circuit
23
This Manual: http://www.manuallib.com/file/2593611
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