DV-CP701
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
BLOCK DIAGRAM
PIN ASSIGNMENTS
PIN NAME TYPE FUNCTION
1 BCK IN Audio Data Bit Clock Input.
(1)
2 DATA IN Audio Data Digital Input.
(1)
3 LRCK IN L-Channel and R-Channel Audio Data Latch En-
able Input.
(1)
4 DGND - Digital Ground
5V
DD
- Digital Power Supply, +3.3V
6V
CC
- Analog Power Supply, +5V
7V
OUT
L OUT Analog Output for L-Channel.
8V
OUT
R OUT Analog Output for R-Channel.
9 AGND - Analog Ground
10 V
COM
- Common Voltage Decoupling.
11 ZEROR/ OUT Zero Flag Output for R-Channel/Zero Flag Output
ZEROA for L/R-Channel.
12
ZEROL/NA
OUT Zero Flag Output for L-Channel/No Assign.
13 MD IN Mode Control Data Input.
(2)
14 MC IN Mode Control Clock Input.
(2)
15 ML IN Mode Control Latch Input.
(2)
16 SCK IN System Clock Input.
NOTES: (1) Schmitt-trigger input, 5V tolerant. (2) Schmitt-trigger with internal
pull-down, 5V tolerant.
PIN CONFIGURATION
TOP VIEW
SSOP
Audio
Serial
Port
Output Amp and
Low-Pass Filter
DAC
4x/8x
Over sampling
Digital Filter
with
Function
Controller
Enhanced
Multilevel
Delta-Sigma
Modulator
Output Amp and
Low-Pass Filter
DAC
BCK
LRCK
DATA
ML
MC
MD
Serial
Control
Port
System Clock
Manager
Zero Detect
Power Supply
V
OUT
L
V
COM
V
OUT
R
V
DD
DGND
ZEROL
ZEROR
SCK
System Clock
V
CC
AGND
BCK
DATA
LRCK
DGND
V
DD
V
CC
V
OUT
L
V
OUT
R
SCK
ML
MC
MD
ZEROL/NA
ZEROR/ZEROA
V
COM
AGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCM1742
1
3
2
15
14
13
16
12
11
5
4
6
9
8
10
7
24-Bit, 192kHz Sampling
Enhanced Multilevel, Delta-Sigma, Audio
Q401: PCM1742KE DIGITAL-TO-ANALOG CONVERTER
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w
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1
6
3
.
c
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m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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