RL78/G13 Safety Function (Frequency Detection)
R01AN0956EJ0100 Rev. 1.00 Page 8 of 70
Feb. 27, 2012
5. Description of the Software
5.1 Operation Outline
The sample code shown in this application note compares the frequencies of the high-speed on-chip oscillator clock and
the low-speed on-chip oscillator clock. This enables detection of any abnormal clock frequencies.
More specifically, the sample code measures the pulse interval under the conditions below to detect an abnormal
frequency.
The high-speed on-chip oscillator clock (HOCO clock) is selected as a count clock for timer array unit 0 (TAU0).
The low-speed on-chip oscillator clock (15 kHz) is selected as a timer input for channel 5 of TAU0.
To judge whether the frequency is normal or abnormal, the pulse interval is checked to see if it is within the tolerable
range specified by constants. If the frequency is normal, the LED1 turns off. If not, the LED1 blinks.
The tolerable range above depends on PULSEWIDTH_RANGE_MIN and PULSEWIDTH_RANGE_MAX in Table
5.
3.
The c
ount clock frequency for TAU0 can be changed dynamically by using the switch. Its frequency depends on
TAU0_COUNT_CLOCK_1 and TAU0_COUNT_CLOCK_2 in Table 5.3. The LED2 turns off when the device
ope
rates with the count clock set by TAU0_COUNT_CLOCK_1. The LED2 turns on when the device operates with the
count clock set by TAU0_COUNT_CLOCK_2.
(1) Initialize the TAU.
Initialize the TAU.
<Conditions for setting>
Select the HOCO clock as a count clock for TAU0.
Select the low-speed on-chip oscillator clock (15 kHz) as a timer input for channel 5 of TAU0.
(2) Start the pulse interval measurement.
The value captured by a first capture end timer interrupt (INTTM05) is invalid. Thus, invalidate the first pulse interval
measurement value according to the following processing:
Disable interrupts.
Set the TS05 bit of timer channel start register 0 (TS0) to 1 to enable counting. This clears the timer count register
(TCR05) to 0000H and starts counting.
Transition to the HALT status and wait until a capture end timer interrupt (INTTM05) occurs.
When the timer input enable edge is detected, the timer counter register (TCR05) value is captured into the timer
data register (TDR05) and then a capture end timer interrupt (INTTM05) will occur. (This results in a return from
the HALT status). Then, clear the timer counter register (TCR05) to 0000H.
Clear the interrupt request flag for INTTM05.
Enable interrupts.
(3) Transition to HALT mode.
Enter the HALT mode and wait until the next enable edge input.
Return from the HALT mode by the processing of the second or subsequent capture end timer interrupt
(INTTM05) or by that of switching external interrupt (INTP0).
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