Performance UM2222
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Figure 19. Performance of STM32H7 Series versus STM32F7 Series
The instruction cache and data cache are enabled in the main.c file as shown in the code
below.
6.2 Multi buffering features
The multiple buffering is the use of more than one frame buffer, so that the display ever
shows a screen that is already completely rendered, even if a drawing operation is in
process. When starting the process of drawing, the current content of the front buffer is
copied into a back buffer. After that, all drawing operations take effect only on this back
buffer. After the drawing operation has been completed, the back buffer becomes the front
buffer. Making the back buffer the visible front buffer normally only requires the modification
of the start address in the frame buffer register of the display controller. Now it must be
considered that the display refreshes a display approximately 60 times per second. After
each period, there is a vertical synchronization signal, known as VSYNC signal. The best
moment to make the back buffer the new front buffer is this signal. If not considering the
VSYNC signal, tearing effects may occur, as shown in Figure 20 below.
06Y9
&38ORDG
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