The 64th character is significant in that the next char-
acter is the start of the next line. When address 63 is
detected, U231 is clocked from state F to state O. The
routine is now back to where it started, and the next line
may
be
displayedin a similarmanner.
State
"F"
data clocks the Display Counter via
CLKRAM, enables U230 and selects its D5 input. AND
gate U223B watches for DisplayCounter address 63; i.e.,
the 64th character. If the 64th character is not detected,
state E is loadedfrom the state F data, resettingCLKRAM
HI in preparationfor the next state F and the associated
CLKRAM pulse.The looping betweenstates E and F con-
tinues to increment the Display Counter until U2238
detects address63 (the 64th character).
State "E" resets the ClKRAM signal from U330 and
disablesU230.The next 5 MHz clock loads state"F" from
state E data.
If EOCH is set LO this time (signaling the last dot),
counter U231 will be loaded to state"D" (instead of
clockedto state 7 as describedearlier).State D clocks the
Display Counter via ClKRAM, enables U230 and selects
its D4 input. This input monitors the EOl signal (X9 bit)
from the Horizontal RAM which will be set HI when the
last character of a given line of readout information has
been displayed.When EOL (end of line) is detected, U231
incrementsto state"E." If it is not detected, state 4 will
be reloadedfrom state D data and the next character will
be displayedas describedbefore.
The next
5MHz
clock loads state 5 from state Band
resets the CKDOTCTC from U330 HI. State 6 is next
loadedfrom state 5 and is once again checkingfor EOCH
(describedearlier).
State "B" is loaded from state"A" and does two
things. It turns RZON off (HI) and sets CKDOTCTC(clock
dot counter) LO, incrementingthe dot counter made up of
U416B and U416A. This addresses the next byte of XY
deflectiondata within U420 in preparationfor the next dot
displaycycle.
State
"8"
is loaded from state 7 and turns on the Z-
Axis via RZON(readoutZ-Axis on) from U330.States"9"
and "A" (hex) are sequentiallyloaded from the previous
state and also have RZONasserted.Thesethree cycles in
sequenceturn the Z-Axis on for 600 ns for each readout
dot to be displayed.
clock. State 7 disables U230, terminating the test
condition.
3-70
State "6" data from U232enablesU230and selects its
D3 input. This is the EOCH(endof character)bit from the
character ROM U420 and will only be LO for the last dot
of any given character. As long as EOCH is HI (not the
last dot), U231 will increment to state
"7"
on the next
State "4" resets CLKRAM HI and disables U230. The
next clock loads state"5," a 200 ns delay,into U231.The
next clock loads state"6."
This next-state data is 2. Returning to state 2 resets
the CLKRAM bit from U330 HI so the next state 3 will
clock the DisplayCounter again.This loop betweenstates
2 and 3 continues to clock the Display Counter until
U223A detects address 11. When this occurs,
COUNT/LOADgoes HI and the next 5 MHz clock incre-
mentsthe state to"4."
State "3" clocks the display RAM (using CLKRAM
from U330),enables U230, and selects its D2input. AND
gate U223A, producing the D2 input level, monitors the
Display Counter address lines, looking for address 11.
Address 11 corresponds to the twelfth character
(remembercharacter 0) and the first character displayed
on the crt. (See Display Output description for further
explanation.)If address 11 has not beenencounteredyet,
the next-state data from U232will be loadedinto U231.
When R/O goes HI, the COUNT/LOADline follows and
the next 5 MHz clock incrementsthe counterto state"2."
State 2 has the LOAD/DECIDEbit set HI, so the next
clock merely loads the next-state data (which happensto
be 3) into U231.
The state 1 data from U232 has the LOAD/DECIDEsig-
nal set LO,and the next three bits selectinput DOof U230
to watch. This is the R/O (readout)line, and it is set HI by
the System J.lPwhen it wants to start a readout display.If
R/O is LO (don't start yet), COUNT/LOADis also LO and
the "next-state" data from U232 is loadedinto counter
U231. For state 1, the next-state data is also 1, so the
state machinejust cyclesin state 1 until R/Ogoes HI.
To go from state"0" to state "1," data from U232 is
loadedinto U231.
data selector U230 is enabled. The three data bits (01
through 03) from U232 definewhich condition needsto be
tested and selectsone of the D inputs of U230to route to
U231 via the COUNT/LOADline. Whether or not the con-
dition being tested for is present at the selected D input
determineswhether counter U231counts or loads.
Theory of Operation-2430 Service
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