When the jitter ramps are reinitiated (in preparation for
the next trigger event), the START1 and STOP1 signals
will return LO. The next rising edge of the 8 MHz clock will
reset the Jitter Correction Counter by clocking pin 6 of
U841A HI.
The System J.LPmay then read the counter contents via
U752 at address-decoded location 620Fh. Counter con-
tents for the B Jitter Correction Counter may be read at
location 620Eh.
The counter increments until the RAMP1 Jitter Correc-
tion circuit detects the discharge threshold has been
crossed. When this occurs, STOP1 (stop counter 1)
applied to U841B will go HI. The next rising edge of the
8 MHz clock disables U851B via U841B and stops the
counter.
Initially, the RAMP1 Counter (composed of U852A and
U852B) is held reset by the HI from pin 6 of U841A. When
the START1 (start counter 1) input goes HI (signaling start
of the slow discharge of integration capacitor C491,
located on diagram 12), the rising edge of the next 8 MHz
clock pulse will enable the counter by clocking the 0 out-
put of U841A LO. The 0 output of the "stop" flip-flop
U841B is LO and enables U851B to pass falling-edge
clock pulses to U852A at an 8 MHz rate.
The RAMP1 Jitter Correction Counter is an eight-bit
counter that is started and stopped by signals from the
RAMP1 Jitter Correction circuit. It counts the 8 MHz clock
pulses over the interval when the Jitter Correction Ramp is
discharging, thus converting the peak value of the ramp to
a binary number. Since that value is directly proportional
to the time difference between a trigger event and the next
sample-clock edge, the number derived by the counter
gives a precise time measurement of where the trigger
occurred with respect to the sampled data. That informa-
tion is used by the System /-!P to correctly place the
random-sampled data points obtained in REPET acquisi-
tion mode with respect to the previously acquired random
data points as the waveform record is filled.
Jitter Correction Counters
The RAMP1 and RAMP2 Jitter Correction Counters
convert the discharge time of their associated Jitter
Correction Ramps to binary numbers relating trigger-event
positions to the edges of the sample clock. Since opera-
tion of both Jitter Correction Counters is identical, only the
RAMP1 Jitter Correction Counter will be described.
3-58
The width of the ATHO pulse represents the time from
which one analog trigger event was accepted to when the
next trigger event is allowed (next acquisition record). By
varying this time (front-panel Holdoff control) the displayed
waveform may be adjusted to exclude undesired trigger
events (which may cause display instability).
As mentioned earlier, propagation delays in the AlB
Trigger Generator and the Trigger Logic Array ensure that
another trigger (ATG) will not occur until 0781 has
discharged the integration capacitors fully to -5 V. This
ensures that holdoff ramps always start from a known
point, and thus maintains holdoff stability.
As the charging ramp reaches the user-defined (front-
panel Holdoff pot) reference level, the output from com-
parator U871 will go LO. This CROSS (reference crossing)
level is applied to U872A and resets the flip-flop. The 0
output, now HI, turns 0781 on and begins discharging the
ramp at a rapid rate. The HI 0 output from U872A
removes the Set level from U872B and allows the ENDHO
(end of holdoff) level from U881 to reset the ATHO level
LO when the discharging ramp reaches -4.6 volts.
When an ATG occurs, the HI level at the input of the
flip-flop is clocked to the 0 output while the 0 output goes
LO. This LO turns 0781 off and allows the selected
current source(s) to charge the capacitors. At the same
time, the LO is applied to pin 10 of U872B, forcing its 0
output HI. This is the ATHO (analog trigger holdoff) signal
and indicates that an analog trigger has occurred. This sig-
nal is applied to AlB Trigger Generator U150 (diagram 11)
to prevent it from recognizing another trigger until the
holdoff time ends.
Initially, the Set and Reset inputs of U872A will be HI,
allowing the flip-flop to watch the ATG (analog trigger) line
for a trigger event. While it is waiting, its 0 output will be
HI, keeping 0781 on and the integration capacitors
discharged.
The Holdoff Logic initiates and controls the holdoff ramp
and produces the holdoff pulse controlling the delay
between one trigger event and the next. It starts the
holdoff ramp when a trigger event is detected, begins ramp
discharge when the user-defined HOREF level is reached,
and ends the holdoff pulse when the ramp crosses the
"end-of-holdoff" level.
Holdoff Logic
Theory of Operation-2430 Service
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