Tektronix PG 508 User Manual

Th eory of O p eration-PG
508
P e r iod Generator
'T h is circuitry generates t he
inter n al perio d timing
wavefor m . In t h is mode, U
140 B o p erates as an astable
multivibrator . Wh en eit h er i n p u t of U 140 B is h ig h
,
pin 7 is
h ig
h
and
pin 6 is low . T he switched ti m i ng cap
acita n ces
a
r e co nn ected from pin 7 to pi n 11 . T h ese ca
p acitors are
switc hed by t h e p erio d range switc
h . T h e p erio d variable
control, R 190, varies t
he resistance in t he n egative
fee d bac k loop .
To start t he p erio d cycle, assume pin 7 of U 140
B goes
h ig h an d p i n 6 low . T h is positive
step, at p i n 7, is couple d
t h roug
h t he period timi ng ca p acito r to pi n 11 . As t he
ti m ing ca p acitor d isc h arges t h ro u g h t he resista nces
con n ecte d from pin 11 to p i n 6, t he
voltage at p i n 11
d ecays at α rate d etermi n ed by
t he timi ng ca p acitor and
t h
ese
resistances . Wh en t he switc h ing level (ap-
proximately 4 V) is reach ed, p i n 7 goes low an d p in 6 goes
h ig h . T he negative ste p , at p i n 7, is couple d th roug
h t he
timing capacitor, and a pp ears at p i n 11 .
T he cap acitor
now ch arges t hroug h t h e resista
n ces un til t he switc h i ng
level
is
reac h ed, and t h e p eriod cycle re p eats . T he
symmetry a dju stme n t com p ensates for t he bias current
t
h
ro
ugh p in 11 .
Wh
e
n
t
h
e
PER IOD switc h is i n any p osition ot h er t han
ΕΧΤ TRIG (MAN), switch S200-2 is ope n ed . T h is lowers
pin 10 of U 140 B and p e r mits t h e p eriod generator to
o p erate du ri ng t h e exte rn al gate on
time . Duri ng t h e time
of t h e
exter n al gati ng sig n al p ins 4 and 2 of U 140A are low .
P i n 3 is h ig h . As transistors 0150 a nd 0160 form α
comparator, wit h t h eir bases con n ecte d to p i ns 3 and 1 of
U 140A res p ectively, t h e collector of Q150 is low
causi ng
t he e m itte r of 0175 to be low, as
well as pi n 11 of U 140 B .
Th
is
allows t h e p eriod generator to o pe r ate . During t he
gate d off time t h is action reverses . P i n 11 of U 140 B rises
a nd i nh ibits t he p erio d generator .
R
esisto
r R 170 an dR 165 a dj ust t h e loc k up voltage at
pi n 11 of U 140 B so t h at, at tur n on, t h e first
perio d
ge n erated is i d en tical in time wit h subse quen t p eriods .
R esistor R 165 is switche d i n to
t he
ci
r cuit
only on
the20 ns
ra n ge . Com
p one n ts R 177 and C177 forma time constant
to
h el p com pen sate for first perio d erro r .
Delay Ge n erator
T h is circuitry p rovi d es t he d elay for d elaye
d
or
paired
p ulse op eratio n . As t h e sig
n al from t h e p eriod generato r of
t
he exte r n al t r igger i npu t goes from h ig h to low at p i n 7 of
U 270 B , p in 3 goes h ig h . T h is causes p i n 5 of U 270A to go
h ig h a n d p i n 2 low . P i n 13 of U 270D and p i n 9 of U 300 B go
low . P in 15 of U 270D goes h ig h bu t pin 10 of U 300
B d oes
n ot follow u ntil about 10 ns
later, d ue to t h e delaying
action of
R 275 a nd C275 . Wh en p i n 9 of U 300 B goes low
p in 6 goes h ig h , assuming pin 11 isalready low . Pin 6stays
2-2
h ig h un til p
i
n 10
goes h ig has descri bed above .
T h
is
action
p rovides t h e d elay gen erator wit h about
α 10 n s trigger
pulse un der all input co n ditio
n
s .
T he
positive-going trigger pu lse, at p
i n 5 of U 300A,
causes pin 3 to go low and pin 2
h ig h . P ositive feed b ac k
th roug h R 300 a nd C300 causes pi
n
4 to
go h ig h . T h e low at
t he base of Q320
tur
ns
Q320 off . T he emitter of Q320 goes
n egative at
α rate determined b y t h e timi ng ca p
acitor and
c u rrent source Q342, wit h its variable
emitte r resista n ces .
As t he emitter of Q320 goes
negative, it p ulls t he base of
Q294 negative w h ic
h lowers p i n 4 of U 300A . Wh en pin 4
reac hes t he switc h ing
t h res h old (~4 .0 V) pi n 2 goes low
an d pin 3
h ig h . T h e timing ca p acito r is now d isc
h arged
t hroug h Q320 . T he monostable d elay ge
n erator is now
reset for t he n ext trigger pulse
. Transistor 0290 provides a
consta n t load for
t he power sup p lies irres p ective of t he
curre
n
t flowi
ng t h roug h Q294 .
Compo n ents R 304, R 306 and C304
provi d e α delay line
for t he CO N TRO L ER
R
OR
lig h t . T he ou p ut from t hedelay
generator is co nn ecte
d
to
pin 13 of U 3000 . P i n 15 of
U 3000 is h ig
h
during
t he d elay time and p i n 14 low .
Gates
U 360 B an dD p rovide α positive-goi ng t
r
igger
at pin 15 of
U 360D w h e n t he d elay
time ends . Gates U 360A a n d C
p rovide α p
ositive-going trigger at p in 14 w hen t he delay
time starts
. As t he d elay time starts, p in 4 of U 360A
goes
low
as does p in 11 of U 360C . P in 10 of U 360C
is low as t he
anode of C R 378 is gro un d ed t
h
roug
h t h e UN D L Y switc h .
T h e low at p in
11
of
U 360C allows pin 14 to go h ig h . P in 14
stays
h ig h until t h e propagation time t h ro u g h gate U 360A
an d t h e delayi
ng actio n of 8364 an d C366 allow t h e
h ig h
ge n erated i n U 360A, from pi n 2, to reset U 360C
t hroug h
p i n 10 . T h is causes pin 14 to retur
n
to
its low state . The
widt h of t h e output
trigger p ulse is about 6 ns .
To obtain
t h e delayed trigger, t he an ode of C
R 378
is
con n ecte d to - Ι --5 V d isabling gate U 360C .
T h ea n ode of
CR 382 is grou n de d throug
h the DL Yswitc h . Gates U 360 B
a nd U 360D now o p
erate in exactly t he same ma nner as
U 360A
an d C . Α positive trigger p ulse a pp ears on pin 15 of
U 360D w hen t he d elay time e nds (pi
n
6 of
U 360 B goes
from h ig h to low) . In
t h e p aired pulse mode bot h gates
operate
. Gate U 360C p rovi d es α positive-going trigger at
t h e start of t he d elay time a nd U 360D α p ositive trigger at
t h e end of t h e d elay time .
Duratio n Generator
T h is
circuitry generates t he d uratio n times .
Gate
U 400 B acce p ts t he d elaye d or u n delayed
positive triggers
from t he d elay generator . T he result is α p
ositive-going
pulse at p i n 5 or U 400A .
T h
is
triggers t he d uration
generator w h ic h operates
in t he same manner as t hed elay
generator .
R efer to t h e d iscussio n un d er t h e h ea d
ing
Delay Ge n e r ator for α d escri p tio n of t
he d uration
generator o p eratio n . Gate U 4000 is an output buffer
. P i n

Tektronix PG 508 Specifications

General

Brand	Tektronix
Model	PG 508
Category	Pulse Generator
Language	English