Xilinx SP701 User Manual

Figure 19: SCUI Graphical User Interface
On the rst use of the SCUI, go to the FMC → Set VADJ → Boot-up tab and click USE FMC
EEPROM Voltage. The SCUI buons are grayed out during command execuon and return to
their original appearance when ready to accept a new command. See the SP701 System
Controller Tutorial (XTP551) and the SP701 Soware Install and Board Setup Tutorial (XTP552)
for more informaon on installing and using the System Controller ulity.
For more details, see the MSP430F5342 data sheet on the Texas Instruments website. The
detailed FPGA connecons for the feature described in this secon are documented in the
SP701 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
FPGA Mezzanine Card Interface
[Figure 2, callout 7]
The SP701 evaluaon board supports the VITA 57.1 FPGA mezzanine card (FMC) specicaon
by providing a low pin count (LPC) FMC connector at J21. LPC connectors use a 10 x 40 form
factor that is parally populated with 160 pins. The connector is keyed so that a mezzanine card,
when installed in the FMC LPC connector on the SP701 evaluaon board, faces away from the
board. The FMC LPC connector pinout is shown in the Appendix A: VITA 57.1 FMC Connector
Pinouts.
FMC LPC Connector J21
[Figure 2, callout 7]
The 160-pin connector J21 implements paral FMC LPC connecvity (refer to schemac
0381874 and the XDC le for details).
Chapter 3: Board Component Descriptions
UG1319 (v1.0) July 12, 2019 www.xilinx.com
SP701 Board User Guide 36
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Xilinx SP701 Specifications

General

Brand	Xilinx
Model	SP701
Category	Motherboard
Language	English