5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Processor 4/7 ( CLK/JTAG/MISC )
FLOAT FOR SKL
GND FOR CNL
CFG7
DEFENSIVE PULL DOWN SITE
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG4
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
EMBEDDED DISPLAY PORT PRESENCE STRAP
CFG2
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG[5:6]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
NEAR CPU
VCCST_PWRGD
CAD Note: Capacitor need to be placed
close to buffer output pin
D02 0626
D02 0701
D02 0706
CFG_RCOMP
H_PECI_R
CPU_VIDALERT#
VCCST_PWRGD
SKL_XDP_MBP_0
SKL_XDP_MBP_1
SKL_MBP_2
SKL_MBP_3
H_TDI
H_TRST#_CPU
H_PREQ#_CPU
H_PRDY#_CPU
VCCST_PWRGD
CFG17
CFG16
CFG19
CFG18
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG11
CFG12
CFG13
CFG14
CFG15
CFG10
CFG0
CFG9
VCCST_PWRGD_CPU
H_PROCHOT#_RH_PROCHOT#
H_PROCHOT#
H_PM_DOWN_R
H_SKTOCC#
H_TCK
H_TMS
H_TDO
H_TDO
H_TCK
H_SKTOCC#
1.0V_VCCST
VCCIO
1.0DX_VCCSTG
3.3VA
1.0V_VCCST
VDD3
1.0V_VCCST
3.3VA
1.0DX_VCCSTG[7,44,52]
VDD3[23,26,29,30,32,35,36,38,39,40,41,43,44,52]
1.0V_VCCST[7,25,26,43,4 5,47]
H_PROCHOT#[45,47,52]
PCH_PECI[25]
PCH_CPU_BCLK_R_DN[28]
PCH_CPU_BCLK_R_DP[28]
PCH_CPU_PCIBCLK_R_DN[28]
PCH_CPU_PCIBCLK_R_DP[28]
CPU_24MHZ_R_DN[28]
CPU_24MHZ_R_DP[28]
H_PWRGD[26]
PLTRST_CPU_N[25]
H_PM_SYNC[25]
H_PM_DOWN[25]
PCH_THERMTRIP#[25]
H_SKTOCC#[2 7]
H_CPU_SVIDCLK[45,47]
H_CPU_SVIDDAT[45,47]
H_CPU_SVIDALRT#[45,47]
H_PROCHOT_EC[39]
H_PECI[39]
DDR_VTT_PG_CTRL[42]
VCCIO[2,3,7 ,43]
ALL_SYS_PWRGD[12,23,39,45,47]
3.3VA[23,24,25,26,27,29,30,38,40,50]
H_TRST# [30]
H_PREQ# [30]
H_PRDY# [30]
Title
Size Document Number Rev
Date: Sheet
of
6-71-N15R0-D02A
2.0A
[05] Processor 4/7-CLK/JTAG/MISC
Custom
562Tuesday, August 18, 2015
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Rev
Date: Sheet
of
6-71-N15R0-D02A
2.0A
[05] Processor 4/7-CLK/JTAG/MISC
Custom
562Tuesday, August 18, 2015
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Rev
Date: Sheet
of
6-71-N15R0-D02A
2.0A
[05] Processor 4/7-CLK/JTAG/MISC
Custom
562Tuesday, August 18, 2015
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
R1353 1K_04
R2086 *0_04
R1356 *1K_04
R1367 *20mil_short_04
R1354 1K_04
R1371 20_1%_04
R1382
1K_04
R1373 *12.1_1%_04
R1369 60.4_1%_04
R1368 *10K_04
R1383
100K_04
R1361 *1K_04
R1385
100K_04
SKYLAKE_HALO
BGA1440
5 OF 14
REV = 1
U137E
SKL_H_BGA_BGA
PROC_SELECT#
BN1
CATERR#
BM30
SKTOCC#
BR33
PM_DOW N
BP31
PM_SYNC
BM34
RESET#
BP35
PROCPWRGD
BT31
VCCST_PWRGD
H13
CFG[17]
BN23
CFG[15]
BT19
CFG[16]
BP23
CFG[11]
BT22
CFG[12]
BM19
CFG[10]
BT23
CFG[9]
BR22
CLK24N
D31
CFG[1]
BN27
CFG[3]
BN28
CFG[18]
BN22
PROC_TDI
BL32
CFG[0]
BN25
CFG[2]
BN26
CFG[4]
BR20
CFG[6]
BT20
CFG[5]
BM20
CFG[7]
BP20
CFG[8]
BR23
CFG[13]
BR19
CFG[14]
BP19
CFG[19]
BP22
PROC_PREQ#
BL30
PROC_PRDY#
BP27
VIDSCK
BH32
PROC_TDO
BT28
CLK24P
E31
PCI_BCLKN
C36
PCI_BCLKP
D35
BCLKN
A32
VIDSOUT
BH29
PROCHOT#
BR30
DDR_VTT_CNTL
BT13
CFG_RCOMP
BT25
PROC_TRST#
BP30
PROC_TCK
BR28
PROC_TMS
BP28
VIDALERT#
BH31
THERMTRIP#
J31
PECI
BT34
BCLKP
B31
BPM#[0]
BR27
BPM#[1]
BT27
BPM#[2]
BM31
BPM#[3]
BT30
R1365 *1K_04
R1366 499_1%_04
R1378 51_04
R1360 *1K_04
R1384 1K_04
R1375 *20mil_short_04
R1349 *1K_04
R1364 *1K_04
R1379 *0_04
R1660 10K_04
R2019 0_04
R1346
*1K_04
R1381
49.9_1%_04
Q62
MTN7002ZHS3
G
DS
R2087 *0_04
R1350 *1K_04
R1362 *1K_04
C1832
*0.1u_10V_X5R_04
R1351 *1K_04
R1348
56.2_1%_04
C956
*0.01u_16V_X7R_04
S
D
G
Q71A
MTDK3S6R
2
61
R1363 *1K_04
R1357
220_04
R2088 *0_04
R1352 *1K_04
S
D
G
Q71B
MTDK3S6R
5
34
R1347
100_04
R1372 51_04
R1359 *1K_04
R1355 1K_04
C957
47P_50V_NPO_04
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