FC_G6
Has well rPGA EDS
9 OF 9
U26I
RSVD
P10
RSVD
U10
NC
B1
VSS
AR26
VSS
AP27
RSVD_TP
E20
RSVD_TP
E21
RSVD
A2
RSVD
E18
RSVD_TP
AR1
RSVD
K6
RSVD
AM2
RSVD
F5
RSVD
AM26
RSVD
AM27
CFG_19
AP23
CFG_17
AP21
CFG_18
AR23
CFG_16
AR21
CFG_RCOMP
AT31
RSVD_TP
D23
RSVD_TP
D24
RSVD_TP
B23
RSVD_TP
C23
CFG_15
AP25
CFG_14
AN26
CFG_13
AN25
CFG_9
AT23
CFG_8
AR24
CFG_7
AN23
CFG_6
AT25
RSVD_TP
B35
RSVD_TP
C35
VCC
F25
RSVD
AL29
RSVD
AL30
RSVD
W33
RSVD_TP
A35
RSVD_TP
A34
RSVD
AD10
RSVD_TP
AT2
RSVD_TP
AT1
CFG_12
AP26
CFG_11
AP24
CFG_10
AN20
RSVD_TP
W29
RSVD_TP
W28
TESTLO
G26
RSVD
AR33
FC
G6
RSVD_TP
AL25
RSVD_TP
W30
RSVD_TP
W31
TESTLO
W34
CFG_0
AT20
CFG_1
AR20
CFG_4
AT22
CFG_5
AN22
CFG_3
AP22
CFG_2
AP20
VSS
AL31
VSS
AL32
H_CPU_RSVD40
R67 *1K_04
R66 *1K_04
R64 *1K_04
R378 *1K_04
R63 *1K_04
R28
*1K_04
Haswell Processor 7/7 ( RESERVED )
CFG3
CFG5
CFG4
CFG2
CFG6
CFG7
R359 49.9_1%_04
R357 49.9_1%_04
R384 49.9_1%_04
(Default)
NOTE:
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
0 : ENABLED SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
1 : DISABLED
(Default)
CFG3
DEFENSIVE PULL DOWN SITE
CFG5
CFG4
CFG2
CFG2
CFG6
CFG[6:5]
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
0: LANE REVERSAL
PCIE Port Bifurcation Straps
11: DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED
10: DEVICE1 FUNCTION1 ENABLED DEVICE1 FUNCTION 2 DISABLED
01: DEVICE 1 FUNCTION 1 DISABLED, DEVICE 1 FUNCTION 2 ENABLED
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED
CFG7
CFG4
CFG Straps for Processor
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0:ENABLED; AN EXTERNAL DISPLAY PORT DEVICE
AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED
TO THE EMBEDDED DISPLAY PORT
VCCI N5,41
VCCIN
PM_PCH_PWROK 22,36
CFG_RCOMP
R68 1K_04
FC_G6
H_CPU_RSVD30
R29
*2K_1%_04
NOTE:
RESERVE THIS CIRCUIT FOR FUTURE COMPATIBILITY
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