8625_GNDA 8625_GNDA
8625_GNDA
8625_GND A
8625_GNDA 8625_GNDA
8625_GNDA
8625_GNDA
8625_GNDA
DAUXp
DAUXn
HPD
DRX1n
DRX1p
DRX0n
DRX0p
C16 0.1u_10V_X7R_04
C10 0.1u_10V_X7R_04
C8 0.1u_10V_X7R_04
C13 0.1u_10V_X7R_04
C15 0.1u_10V_X7R_04
EDP_TXN_06
DP_AUXP6
C17 0.1u_10V_X7R_04
EDP_TXP_16
EDP_TXN_16
DP_AUXN6
EDP_TXP_06
EDP_HPD6,12
R18
*100K_04
R9 1K_04
BRIGHTNESS36
LVDS-U2N 12
LVDS-LCLKN 12
LVDS-U2P 12
LVDS-LCLKP 12
LVDS-L2N 12
LVDS-U1P 12
LVDS-L2P 12
LVDS-L1P 12
LVDS-L0P 12
LVDS-U1N 12
LVDS-UCLKP 12
LVDS-L1N 12
LVDS-L0N 12
LVDS-UCLKN 12
LVDS-U0P 12
LVDS-L1P
LVDS-L1N
LVDS-U0N 12
LVDS-LCLKP
LVDS-LCLKN
LVDS-L2P
LVDS-L2N
LVDS-U2N
LVDS-U1P
LVDS-U1N
LVDS-L0P
LVDS-L0N
LVDS-U0P
LVDS-U0N
LVDS-UCLKP
LVDS-UCLKN
LVDS-U2P
P_DDC_DATA 12
PANEL_PWM 12
ENBLT 12
PANEL_VCC_EN 12
P_DDC_CLK 12
SMD_EDO_DAT36
SMC_EDP_CLK36
VDDIO
U1
PS8625
SW_OUT
15
SW_OUT
16
GNDX
17
GNDX
18
VDD12
19
TESTMODE
20
RLV_LNK/GPIO0
21
RLV_CFG
22
ENBLT
23
CSDA/MSDA
24
CSCL/MSCL
25
REXT
26
BLV_AMP
27
GND
28
TA1n
42
TA1p
41
TB1n
40
TB1p
39
VDDIO
38
TC 1n
37
TC 1p
36
TC K1 n
35
TC K1 p
34
ENPVCC/I2C_ADDR
33
TD 1n
32
TD 1p
31
DDC_SDA
30
DDC_SCL
29
NC
56
NC
55
TA0n
54
TA0p
53
TB0n
52
TB0p
51
VDDIO
50
TC0n
49
TC0p
48
TCK0n
47
TCK0p
46
PWMI
45
TD0n
44
TD0p
43
DAUXn
1
DAUXp
2
GND
3
DRX0p
4
DRX0n
5
VDDRX
6
DRX1p
7
DRX1n
8
RST#
9
PD#
10
HPD
11
PWMO
12
VDDI OX
13
VDDI OX
14
Epad
57
LVDS-U1P
LVDS-U1N
LVDS-U0P
LVDS-U0N
P_DDC_DATA
PANEL_VCC_EN
LVDS-UCLKP
LVDS-U2P
LVDS-U2N
LVDS-L1P_L
DRX0p
LVDS-L1N_L
LVDS-L0P_L
LVDS-L0N_L
RST#
DRX1n
DRX0n
DRX1p
LVDS-L2P
VDDIOX
VDDIOX
HPD
PD#
P_DDC_CLK
PANEL_PWM
LVDS-LCLKP_L
VDDIO
VDD12
LVDS-LCLKN_L
SW_OUT
SW_OUT
VDDRX
LVDS-L2N
ENBLT
RLV_CFG
GND
GND
BRIGHTNESS_EC_PS
SMC_EDP_CLK
RLV_LNK/GPIO0
SMD_EDO_DAT
C4
4.7u_6.3V_X5R_06
Noe:
R13: LVDS output swing control
4.99K f or def ault swing, change the v alue for swing adjus t
RLV_AMP
REXT
DAUXp
DAUXn
Note:
The decoupling caps C9, C15, C16, C17, C18, C21
shall be close to the power pins as possible
LVDS-UCLKN
VDD12SW_OUTVDDIOX
C14
4.7u_6.3V_X5R_06
VDDRX
1. Place the switching regulator inductor (L3) close to SW_OUT Pins (Pin15, Pin16).
2. The SW_OUT output traces sho uld be as wide as possible.
3. The GND X pins (Pin17, Pin18) should be connected to the main PCB gro und plane, with the device GND pins of the PS8625 conn ected to separate GND island (GNDA) for the device.
The GND island (GNDA) should be connected to the main GND plane (GND) with a single-point connection by use of a wide PCB trace.
4. Place the 4.7uF decoupling Capacitor (C4) for VDDIOX close to VDDIOX pin.
5. The GND of the 4.7uF capacitor (C4) for VDDIOX should be placed close to the GND of 4.7uF capacitor (C5) behind Inductor.
6. Plac e the bead (L 2) fo r VD DI OX cl os e to PS8 62 5.
RST#
PD#
VDDIO
PANEL_VCC_EN
ENBLT
VDDIO
PANEL_PWM
To LVDS Connector
P_DDC_CLK
Single link
LVDS
P_DDC_DATA
I2C_CFG = "H"
EEPROM f or Initial Code
I2C Address: 0xA0
Suggest minimum 2Kbit
Initial
Code
EEPROM
Dual link
LVDS
Close to C17
6-03-08625-030
Power On Configuration
I2C_ADDR: I2C Slav e address selection, internal pull-down ~80K
L: 0x10h~0x1Fh
H: 0x 90h~0x9Fh
VDDIOPANEL_VC C_EN
Close to C15
Close to C13
Close to C16
RLV_CFG: LVDS color depth and data mapping selection, internal pull-down ~80K
L: 8-bit LVDS, VESA mapping
M: 8-bit LVDS, JEIDA mapping
H: 6-bit LVDS, both VESA and JEIDA mapping
GND VDDIO
Close to C10
Close to C8
single
PCB
trace
C7
0.1u_16V_Y5V_04
C19
0.1u_16V_Y 5V_04
C12
0.1u_16V_Y5V_04
C1
0.1u_16V_Y5V_04
C2
0.01u_16V_X7R_04
C11
0.01u_16V_X7R_04
R1 4.99K_1%_04
R2 4.99K_1%_04
C9
1u_6.3V_X5R_04
C5
1u_6.3V_X5R_04
C6
2.2u_6.3V_X5R_04
C18
1u_6. 3V_X5R_04
C3
0.47u_10V_Y5V_04
C20
0.47u_10V_Y 5V_04
L4
HCB1005KF-121T20
L3
HCB1005KF-121T20
L1
HCB1005KF-121T20
R13
10K_04
L2
BCNR3010C-2R2M
1 2
R15
10K_04
R20 4.7K_04
R19 4.7K_04
3.3VS
3.3VS
3.3VS
eDP®ÉR115,R167,R168,R212,R228,R229¤W¥ó
eDP®ÉC10,C8¤£¤W¥ó
eDP®ÉC15,C13¤£¤W¥ó
eDP®ÉR9¤£¤W¥ó
eDP®ÉC17,C16¤£¤W¥ó
JP1
*15mil_short_06
BRIGHTNESS_EC_PS
L_BRIGHTNESS_R23
D2RB751S-40C2
A C
D25*RB751S-40C2
A C
LVDS-LCLKN_R 12
LVDS-LCLKP_R 12
LVDS-L0P_R 12
LVDS-L0N_R 12
EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
LVDS-L1P_R 12
LVDS-L1N_R 12
VDDIO
VDDIO12
RLV_LNK/GPIO012
RLV_LNK/GPIO0
RLV_LNK: LVDS single link or dual link selection, internal pull-down ~80K
L: Single link LVDS
H: Dual link LVDS
LVDS-LCLKP_R
LVDS-LCLKN_R
LVDS-L0P_R
LVDS-L0N_R
LVDS-L1P_R
LVDS-L1N_R
DP_AUXP
DP_AUXN
3.3VS3,6,9,10,12,19,20,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,41
C359
*4.7u_6.3V_X5R_06
R247 0_04
LVDS®ÉR244,R247,R248,R249,R250,R251¤W¥ó
R249 0_04
R244 0_04
R155 *0_04
R248 0_04
R167 *0_04
Close to J_LCD1
R168 *0_04
R212 *0_04
R228 *0_04
R253 0_04
R229 *0_04
R254 0_04
LVDS-L0P_L
LVDS-L0N_L
LVDS-L1P_L
LVDS-L1N_L
LVDS-LCLKN_L
LVDS-LCLKP_L
R14 *4.7K_04
R6 4.7K_04
RLV_CFG
R5 *4.7K_04
8625_GND A
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