Intel Arria 10 series User Manual

Figure 6. Components Required for RX or TX Only Design
Parallel Data
Serial Data
Avalon-MM
Control and Status
0
Removed RX TX
I
2
C Slave
(EDID)
PIO
I
2
C Slave
(SCDC)
EDID RAM
RX Core
RX
Oversampler
DCFIFO
RX Core Top
IOPLL
Transceiver PHY
Reset Controller
RX Native PHY
RX Reconfiguration
Management
IOPLL
Reconfiguration
Transceiver
Arbiter
CPU Sub-System
RX-TX Link
I
2
C
Master
PIO
TX Core
TX
Oversampler
Clock Enable
Generator
DCFIFO
TX Core Top
TX PLL
Transceiver PHY
Reset Controller
TX Native PHY
IOPLL
Reconfiguration
IOPLL
RX Audio
RX Video
RX Auxiliary
RX Sideband
TX Audio
TX Video
TX Auxiliary
TX Sideband
RX Top TX Top
Top
Note: If your design only requires HDMI TX or retransmitting HDMI stream from RX to TX
through video frame buffer, supply the TX PLL reference clock directly from an
external programmable oscillator. Intel recommends that you do not cascade IOPLL to
TX PLL.
Related Links
Jitter of PLL Cascading or Non-Dedicated Clock Path for Arria 10 PLL Reference Clock
Refer to this solution for workaround if your design clocks experience additional
jitter.
2.2 Design Components
The Intel FPGA HDMI IP core design example requires these components.
Table 7. HDMI RX Top Components
Module Description
RX Core Top The RX Core top level consists of:
continued...
2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
13

Intel Arria 10 series Specifications

General

Brand	Intel
Model	Arria 10 series
Category	Motherboard
Language	English