Intel Arria 10 series User Manual

B Revision History for Intel FPGA HDMI Design Example
User Guide for Intel Arria 10 Devices
Date Version Changes
November 2017 2017.11.06 • Renamed HDMI IP core to Intel FPGA HDMI as per Intel rebranding.
• Changed the term Qsys to Platform Designer.
• Added information about Dynamic Range and Mastering InfoFrame (HDR)
insertion and filtering feature.
• Updated the directory structure:
— Added script and sofware folders and files.
— Updated common and hdr files.
— Removed atx files.
— Differentiated files for Intel Quartus Prime Standard Edition and Intel
Quartus Prime Pro Edition.
• Updated the Generating the Design section to add the device used as
10AX115S2F4I1SG.
• Edited the transceiver data rate for 50-100 MHz TMDS clock frequency to
2550-5000 Mbps.
•
Updated the RX-TX link information that you can release the user_pb[2]
button to disable external filtering.
• Updated the Nios II software flow diagram that involves the controls for
I
2
C master and HDMI source.
• Added information about the Design Example GUI parameters.
• Added HDMI RX and TX Top design parameters.
• Added these HDMI RX and TX top-level signals:
—
mgmt_clk
—
reset
—
i2c_clk
—
hdmi_clk_in
— Removed these HDMI RX and TX top-level signals:
•
version
•
i2c_clk
• Added a note that the transceiver analog setting is tested for the Intel
Arria 10 FPGA Development Kit and Bitec HDMI 2.0 Daughter card. You
may modify the analog setting for your board.
continued...
UG-20077 | 2017.11.06
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
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Intel Arria 10 series Specifications

General

Brand	Intel
Model	Arria 10 series
Category	Motherboard
Language	English