Intel Arria 10 series User Manual

Figure 2. Directory Structure for the Design Example
<Design Example>
* Standard = Intel Quartus Prime Standard Edition
Pro = Intel Quartus Prime Pro Edition
quartus
incremental_db (Standard)
db (Standard)/qdb (Pro)
output_files
tmp-clearbox (Pro)
a10_hdmi_demo.qpf
a10_hdmi_demo.qsf
rtl
nios.qsys
gxb
hdmi_rx
hdmi_tx
i2c_master
i2c_slave
reconfig_mgmt
sdc
hdr
common (Pro)
pll
rxtx_link.v
a10_hdmi2_demo.v
a10_reconfig_arbiter.sv
clock_control.qsys/clock_control.ip
clock_crosser.v
script
build_ip.tcl
build_sw.sh
runall.tcl
tx_control_bsp
tx_control
tx_control_src
software
simulation
aldec
cadence
mentor
synopsys
hdmi_rx
hdmi_tx
autotest_crc.v
bitec_hdmi_audio_gen.v
bitec_hdmi_tb.sv
tpg.v
Table 1. Generated RTL Files
Folders Files
gxb •
/gxb_rx.qsys (Intel Quartus Prime Standard Edition)
•
/gxb_rx.ip (Intel Quartus Prime Pro Edition)
•
/gxb_rx_reset.qsys (Intel Quartus Prime Standard Edition)
•
/gxb_rx_reset.ip (Intel Quartus Prime Pro Edition)
•
/gxb_tx.qsys (Intel Quartus Prime Standard Edition)
•
/gxb_tx.ip (Intel Quartus Prime Pro Edition)
•
/gxb_tx_fpll.qsys (Intel Quartus Prime Standard Edition)
•
/gxb_tx_fpll.ip (Intel Quartus Prime Pro Edition)
•
/gxb_tx_reset.qsys (Intel Quartus Prime Standard Edition)
•
/gxb_tx_reset.ip (Intel Quartus Prime Pro Edition)
hdmi_rx •
/hdmi_rx.qsys (Intel Quartus Prime Standard Edition)
•
/hdmi_rx.ip (Intel Quartus Prime Pro Edition)
/hdmi_rx_top.v
/mr_clock_sync.v
/mr_hdmi_rx_core_top.v
/mr_rx_oversample.v
/symbol_aligner.v
hdmi_tx •
/hdmi_tx.qsys (Intel Quartus Prime Standard Edition)
•
/hdmi_tx.ip (Intel Quartus Prime Pro Edition)
/hdmi_tx_top.v
continued...
1 Intel
®
FPGA HDMI Design Example Quick Start Guide for Intel
®
Arria
®
10 Devices
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
4

Intel Arria 10 series Specifications

General

Brand	Intel
Model	Arria 10 series
Category	Motherboard
Language	English