Name: Intel i960 Series
Brand: Intel
Rating: 4 (1 reviews)

Default Chapter3

Table of Contents3

Chapter 1 Introduction18

Chapter 2 Getting Started21

Chapter 3 Hardware Reference29

Connectors, Switches and Leds31
Table 3-1 External Connectors and Leds32
Cpu Modules33
- CPU Module Installation33
- CPU Module Clock Frequencies33
- Table 3-2 CPU Module Frequency Switch Settings33
- I960 Jx/Hx CPU Counter/Timers34
- CPU Module VPP Switch34
Cpu Memory Map34
Table 3-3 I960 Jx/Hx CPU Clock Rates34
Interleaved Dram35
- DRAM Performance35
- Upgrading SIMM DRAM36
- Table 3-4 DRAM Access Times36
Flash Memory37
- Swaprom Switch37
- Table 3-5 DRAM SIMM Configurations37
- Table 3-6 Flash ROM Addresses37
Interrupts38
Table 3-7 Interrupt Sources38
Table 3-8 80960Sx and Kx Interrupt Sources38
Console Serial Port39
Table 3-9 80960Sx and Kx Interrupt Switch Settings39
Table 3-10 UART Register Addresses39
Parallel Port40
- Parallel Port Bit Assignments40
- Table 3-11 Parallel Port Addresses40
- Table 3-12 Parallel Port Status Register Bit Assignments40
Z8536 Counter I/O Unit (Cio)41
- Counter/Timers41
- Table 3-13 Parallel Port Control Register Bit Assignments41
- Table 3-14 CIO Register Address41
- CIO Port a42
- CIO Port B43
- CIO Port C44
Non-Volatile Parameter Memory44
Squall II Module Interface44
Table 3-17 Available Squall II Modules45
Table 3-18 Squall Module Compatibility at Maximum CPU Clock Speed (33 Mhz)45
PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)46
- PCI 9060 Configuration46
- Local-To-PCI Configuration54
- Table 3-28 Local Range Register for Direct Master-To-PCI Description55
- Table 3-29 PCI Base Address (Re-Map) Register for Direct Master-To-PCI Description55
- Table 3-30 Local Bus Base Address Register for Direct Master-To-PCI Memory56
- Table 3-31 Local Base Address for Direct Master-To-PCI IO/CFG Register56
- Deadlock Configuration57
- Table 3-32 PCI Configuration Address Register for Direct Master-To-PCI IO/CFG57
- Signalling Init Done58
- PCI Interrupts58
  - Local PCI Interrupts59
  - Table 3-33 Interrupt Control/Status59
- Mailbox Registers and Doorbell Interrupts61
- DMA Programming62

Chapter 4 Theory of Operation65

Chapter 5 Squall II Module Interface77

Appendix A97

Brand	Intel
Model	i960 Series
Category	Computer Hardware
Language	English

Intel i960 Series User Manual

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