rate which means, each digit is on for lms. Each update
begins by presenting new segment information on the VIA
(I/O) bus (PAO-PA7) end outputting a clock pulse on CA2.
The clock pulse inputs to U203 and shifts a digit enable bit
to the next digit to be enabled. Every eight times the display
is updated, a digit enable bit is generated at PB5 and goes to
the enable data input of the shift register.
The first four digit drivers drive the rows of the switch
matrix. The switches are arranged in a four by six matrix.
The segment drivers are D201 through D208. In addition to
driving the various segments, they also activate the appro-
priate LEDs.
MEMORY
ADDRESS l”EX,
woo
Figure 4-3. Memory Map
4-514-6
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