Quectel RG50-Q Series User Manual

5G/LTE-A Module Series
5G EVB User Guide
5G_EVB_User_Guide 28 / 38
3.8. UART Interfaces (J2002/J2003)
The 5G EVB supports two UART interfaces: main UART J2002 and debug UART J2003, supporting baud
rate of 115200 bps by default.
The main UART interface is used for communication between the module and the host application.
The debug UART interface is used for Linux console and log output.
The following figure shows a block diagram of UART interfaces of the EVB.
J0101
Module
Main UART
1.8V
U2001
RS232
Transceiver
3.3V/1.8V
Level Shift
J2002
RS232
1.8V
U2003
3.3V/1.8V
Level Shift
Q2001 Q2002
USB to
UART
Bridge
J2003
U2005
Debug UART
Figure 22: UART Block Diagram
3.9. PCIe to USB Interface (J1601)
The 5G EVB reserves a PCIe 3.0 signal over USB interface for developers’ testing, and this function is not
enabled by default. Please refer to the following block diagram.
J0101
Module
J1601
PCIe
Switch
U1501/U1701
CLK
TX0/1
RX0/1
WiFi
AP
USB3.0B
USB3.0 A<->B cable
SEL_1
SEL_2
Figure 23: PCIe Block Diagram

Quectel RG50-Q Series Specifications

General

Brand	Quectel
Model	RG50-Q Series
Category	Control Unit
Language	English