Radio Shack Quick Printer II Reference Handbook

Video RAMs
The Video RAMs are static and do not need
refreshing.
The data bus is wired in the same
way as system RAMs, but with a different
enable signal.
One interesting point to note: There are seven
RAMs. Six are used
for ASCII storage, and the
seventh is used as a graphic/alphanumeric defi-
nition bit. There are eight data lines. Notice the
line labeled Bit 6. It is sourced by NOR gate
230 at pin 13. If Bit 5 (262, pin 12) and Bit 7
(263, pin 12) are low, then Bit 6 will be high.
Z30 is a sneaky way of squeezing a seventh
ASCI·I bit out of six RAMs.
Aside from
the data bus, there is another RAM
output for data. The Video Processor needs
video
data for generation of the alphanumeric
and graphic symbols. And this section will be
discussed
next.
Video Processing
Video Processing consists of five subsections.
They are: Data Latch, Character/Graphic
Generator, Shift Register, Sync Generator, and
Video Mixing/Output driver.
The Data Latch temporarily stores an ASCII or
graphic word from Video RAM. The Latch will
retain
the byte for processing so that the RAM is
free to search out the next byte. The Character
Generator is a ROM that is addressed by the
Data Latch and the scan line signals. This ROM
contains the alphanumeric format that makes
up all the characters. The Graphic Generator is
not a ROM, but a 4-line-to-1-line data multi-
plexer. It
operates somewhat like a "bit steering"
circuit. It steers an ASCII word into a graphics
symbol. The Shift Register accepts data from
the character generator (or the graphics gen-
34
eratorl and converts parallel dot data into serial
dot data. Meanwhile, the Sync Generator cir-
cuits have been accepting timing signals from the
divider chain. The Sync Circuits shape up the
horizontal and vertical pulses, serrate the verti-
cal interval
and send it all out to video mixing in
serial
format. In the Video Mixing section, the
serial dot video and the serial sync are brought
together. The resulting composite video signal
is then "fine tuned" in amplitude and dot-to-
sync ratio, and then buffered for a 75 ohm out-
put cable. The signal leaves the TRS-80 and is
applied to the Video Display. In the Display,
the signal is torn apart into its separate compo-
nents; and you have a readable image on the
screen.
Data Latch
The Data Latch consists of 228 for the ASCII
and Z27 for the graphic bit and blanking signals.
The inputs of Z28 come from the six Video
RAMs.
The outputs of 228 go to 229, the alpha-
numeric Character Generator and to 28, the
Graphics Generator. The inputs which control
228 are on pin 9 (latch) and pin 1 (VCLR*l.
The latch signal at pin 9 is a pulse train develop-
ed by
the divider-chain-input-conditioning logic.
This signal goes low every six
dot cycles (see
Figure 5
for latch timing). On the rising edge of
latch (low to high transaction), ASCII data in
RAM is transferred to the outputs and temporar-
ily stored by Z28. RAM data at the input to Z28
may now change, and the RAM has time to
search for the next ASCII character.
Note: RAM, any RAM, has a parameter called
"Access
time". This is the time it takes for the
data output to reflect a change after an address
change.
For example, assume a RAM output is
high. The address of the RAM is changed to a
new location where a
"0" data bit is stored.
Even though the RAM is now addressing the low
cell,
the output still reads the previous high.
Only after a short length of time (in the nano-
seconds) will
the output change from a high to
a low.

Radio Shack Quick Printer II Specifications

General

Brand	Radio Shack
Model	Quick Printer II
Category	Desktop
Language	English