Explanation of
Expansion
Port
Signals
The
table
on
the
facing page lists
all
the
Expan-
sion
Port
pin
connections
and signal names.
Figure 22 shows
the
connection
points
as
they
exist on
the
back
of
the
Logic
PCB.
The
follow-
ing detailed description
of
the
various signals
will aid
you
in understanding (and using)
the
Expansion Port.
Address
Output:
There
are 16
of
these lines,
labeled
Ar/J
thru
A
15.
Ar/J
is
the
least signifi-
cant
bit, and A15
is
the
most
significant bit.
These
outputs
form
the
address bus from
the
TRS-80 microprocessor. If you
monitor
these
lines, you would know exactly where
in
memory
the
CPU was reading
or
writing data.
The
address bus can address up
to
65,536
different
memory
locations (2
16
= 65,536).
Each line will drive
only
one
TTL
load.
Bi-directional Data Bus:
There
are 8
of
these
lines, labeled
Dr/J
thru
07.
Dr/J
is
the
least
significant
bit
and D7
is
the
most
significant
bit.
The
CPU
uses
the
data
lines
to
move
binary
data
from
one
section
to
another
sec-
tion
in
the
Computer. Since this bus
is
bi-
directional
you
should use tri-state buffers for
input
and
output
data
moves.
Row Address
Strobe
Output:
This line
is
labeled
RAS*. It
is
normally high and goes low
only
when
the
CPU
is
outputting
the
ROW
por-
tion
of
the
address. It
is
used
to
address
dynamic RAMS. (See
RAM
Addressing
in
text
for
operation.)
Column Address
Strobe
Output:
This line
is
labeled CAS*. It
is
normally high and goes
low only when
the
CPU
is
outputting
the
column
portion
of
an address. It
too
is
used
to
address Dynamic RAMS. (See
text
for
operation.)
90
Multiplexer
Control
Output:
This
output
is
labeled MUX. It
is
used
to
select
the
proper
address line in
conjunction
with RAS* and
CAS* for
the
RAMS. (See
text
for opera-
tion.)
System Reset
Output:
This
output
is
labeled
SYSRES*. It goes low
only
when
the
Reset
button
is
pressed,
or
upon
power
up. It can
be used
to
reset external devices
at
the
same
time
as
the
TRS-80
is
reset. Normally it will
be high.
Test
Input:
This line
is
labeled TEST*. When
taken
low it will tri-state
the
data.
the
address
and
the
control group buffers. Normally, it
will
not
be used by external circuits. Jt
is
used
only
during
factory
testing and in
some
cases
during troubleshooting.
Processor Wait: When taken low, WAIT* will
pause
the
CPU from
further
processing until
WAIT* goes back high.
In
some cases an ex-
ternal device may need
time
to
gather data.
The
WAIT*
input
will give
the
external device
the
time it needs.
Memory Write
Strobe:
When WR* goes low,
the
CPU
is
writing
the
data
present
on
the
data
bus into
the
memory
specified by
the
address
bus. It
is
normally high.
Memory Read
Strobe:
When R
D*
goes low.
the
CPU
is
reading data present on
the
data
bus
from
the
memory
location specified by
the
address bus. It
is
normally high.
Peripheral Write
Strobe:
OUT* operates some-
what
like WR*;
except
OUT*
is
a
port
func-
tion. When OUT* goes low,
data
present
on
the
data
bus
is
meant
to
be received by
the
port
specified by
the
8 lower
order
bits
in
the
address
bus,
A0
thru
A7.
The
Z80
can
address
up
to
256
output
ports.
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