Level II
ROMs
One
of
the most fascinating
aspects
of
a compu-
ter
is
its versatility.
It
can
do almost anything;
all
it
needs
to
know
is
how. With a single
ROM
change, the
TRS-80
can
speak
in any higher level
language
we might
care
to
use.
In Level I we
had
just enough mathematical
and
symbolic capabil-
ities
to
inspire bigger and better things.
The difference between a Level I
TRS-80
and a
Level
II
TRS-80
is
inspiration and a bigger ROM.
Level I
uses
4K
of
ROM. In Level
II,
the system
uses
12K
of
ROM. The added
8K
of
ROM
is
enough
to
give
text
editing; transcendental func-
tions; giant numeric and string arrays; and more
system variables than you
can
use.
The guts
of
the system
have
not
changed and the hardware
is
the
same.
The only difference
is
the machine
language
contained in ROM.
A Level II machine
can
be
identified
by
a
sep-
arate ROM Board
that
is
stuck
to
the etched side
of
the
CPU
Board. This Board contains three
4K
ROMs, a
TTL
decoder, and a ribbon cable. The
cable attaches the
majority
of
the ROM's
ad-
dress
inputs and all
of
the data outputs
to
the
now
empty main Board ROM sockets.
There
is
also
a
4-conductor
ribbon cable (green,
orange,
red
and yellow) coming
from
the
Level
II Board. The conductors connect
to
the
CPU
Board at
A11, A12,
A13 and ROM*. The con-
ductors enable a Level I
to
Level II conversion
on any level production Board quite painlessly.
Note:
If
you
have
a
different
configuration
for
your
Level II machine, refer
to
the
Schematics
section
of
th
is
book
for
later versions (Revisions
D, E and G).
A
11
is
used
as
an
address
for
all three
of
the
ROMs.
It
is
tied
to
pin 18
of
Z1, Z2
and
Z3.
A 12 and A 13's
leads
go
to
the
A(/)
and
A 1 inputs
to
decoder, Z4.
Z4
is
an
addition
to
the address
decoder network on the main Board.
When
A 12 and A 13
are
(/)(/),
pin 1
of
Z4
goes
low
and
ROM
A
is
enabled. When A 12
and
A 13
are
(/)1,
ROM B
is
selected;
and
when A 12
and
A 13
are
1
(/),
ROM
C
is
selected
by
a low at pin 3.
Since
we
want the ROMs
to
be
accessed
only
when the
CPU
needs
instruction,
ROM*
is
there-
fore brought
into
Z4
to
act
as
a master enable.
Only
when
ROM*
is
low
will
we
ever select
ROM
A through
ROM
C.
ROM
power,
minor
ROM
addressing and data
output
are
handled by the large ribbon cable.
One end
of
this cable
is
connected
to
the socket
of
the ROM Board, while the other end
is
at-
tached
to
Z31's socket. Addressing and data
outputs
are
handled
by
the
same
circuits
that
support Level
I.
55
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