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9.3 Port and Bit Assignments
PORT
E8H
OUTPUT:
MASTER RESET
INPUT:
MODEM STATUS REGISTER
An output to this port (and data), performs a master reset to the UART and enables the control register load enable
bit. The following table details the bit definitions for an input from port E8H.
DATA BIT FUNCTION
D7 Clear To Send, Pin 5 DB-25
D6 Data Set Ready, Pin 6 DB-25
D5 Carrier Detect, Pin 8 DB-25
D4 Ring Indicator, Pin 22 DB-25
D3 Not Used
D2 Not Used
D1 Not Used
D0 Receiver Input, UART Pin 20 DB-25
PORT
E9H
OUTPUT:
BAUD RATE LOAD
INPUT:
NOT USED
An output to this port loads the Baud rate generator with a code which corresponds to the desired receive and
transmit Baud rate as outlined in the BRG Programming Table. The low order nibble of the data output to this port
determines the receiver Baud rate, while the high order nibble determines the transmit Baud rate.
PORT
EAH
OUTPUT:
UART AND MODEM CONTROL
INPUT:
UART STATUS
An output to this port loads the UART Control register if the enable bit for this function is set (D1 port E8H = 1). The
UART Control register is five bits wide (D7 - D3) leaving three bits for modem control (D2 - D0). Three more
modem control bits were added by allowing software to enable or disable the UART Control register. The tables
below summarize the bit allocations with the UART Control register enabled and disabled.
PORT EAH OUTPUT BITS WITH UART CONTROL REGISTER ENABLED
DATA BIT FUNCTION
D7 Even Parity Enable, 1 = even, 0 = odd
D6 Word Length Select 1
D5 Word Length Select 2
D4 Stop Bit Select, 1 two stop bits, 0 = one stop bit
D3 Parity Inhibit, 1 = disable parity
D2 Break 0 = disable transmit data (continuous space)
D1 Data Terminal Ready, Pin 20 DB-25
D0 Request To Send, Pin 4 DB-25