Radio Shack TRS-80 Model 4 Technical Reference Manual

26
3.2 Model 4 I/O Bus
The Model 4 Bus is designed to allow easy and
convenient interfacing of I/O devices to the Model 4.
The I/O Bus supports all the signals necessary to
implement a device compatible with the Z-80s I/O
structure. That is:
Addresses:
A0 to A7 allow selection of up to 256
†
input and
256 output devices if external I/O is enabled.
†
ports 80H to 0FFH are reserved for System use.
Data:
DB0 to DB7 allow transfer of 8-bit data onto the
processor data bus if external I/O is enabled.
Control Lines:
a. IN* - Z-80 signal specifying that an input is in pro-
gress. Gated with lORQ.
b. OUT* - Z-80 signal specifying that an output is in
progress. Gated with IORQ.
c. RESET* - system reset signal.
d. IOBUSINT* - input to the CPU signaling an inter-
rupt from an I/O Bus device if I/O Bus interrupts
are enabled.
e. IOBUSWAIT* - input to the CPU wait line allow-
ing I/O Bus device to force wait states on the Z-
80 if external I/O is enabled.
f. EXTIOSEL* - input to CPU which switches the
I/O Bus data bus transceiver and allows an
INPUT instruction to read I/O Bus data.
g. M1* - and IORQ* - standard Z-80 signals. . . .
The address line, data line, and control lines a to c
and e to g are enabled only when the ENEXIO bit in
EC is set to a one.
To enable I/O interrupts, the ENIOBUSINT bit in the
CPU IOPORT E0 (output port) must be a one.
However, even if it is disabled from generating
interrupts, the status of the IOBUSINT* line can still
read on the appropriate bit of CPU IOPORT E0 (input
port).
See Model 4 Port Bit assignment for port 0FE, 0EC,
and 0E0 on pages 28 and 29.
The Model 4 CPU board is fully protected from
“foreign I/O devices” in that all the I/O Bus signals are
buffered and can be disabled under software control.
To attach and use an I/O device on the I/O Bus,
certain requirements (both hardware and software)
must be met.
For input port device use, you must enable external
I/O devices by writing to port 0ECH with bit 4 on in
the user software. This will enable the data bus
address lines and control signals to the I/O Bus edge
connector. When the input device is selected, the
hardware will acknowlege by asserting EXTIOSEL*
low. This switches the data bus transceiver and
allows the CPU to read the contents of the I/O Bus
data lines. See Figure 3.6 for the timing. EXTIOSEL*
can be generated by NANDing IN and the I/O port
address.
Output port device use is the same as the input port
device in use, in that the external I/O devices must be
enabled by writing to port 0ECH with bit 4 on in the
user software - in the same fashion.
For either input or output devices, the IOBUSWAIT
control line can be used in the normal way for
synchronizing slow devices to the CPU. Note that
since dynamic memories are used in the Model 4, the
wait line should be used with caution. Holding the
CPU in a wait state for 2 msec or more may cause
loss of memory contents since refresh is inhibited
during this time. It is recommended that the
IOBUSWAIT* line be held active no more than 500
µ
sec with a 25% duty cycle.
The Model 4 will support Z-80 mode 1 interrupts. A
RAM jump table is supported by the LEVEL II BASIC
ROMs and the user must supply the address of his
interrupt service routine by writing this address to
locations 403E and 403F. When an interrupt occurs,
the program will be vectored to the user supplied
address if I/O Bus interrupts have been enabled. To
enable I/O Bus interrupts, the user must set bit 3 of
Port 0E0H.

Radio Shack TRS-80 Model 4 Specifications

General

Brand	Radio Shack
Model	TRS-80 Model 4
Category	Desktop
Language	English