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3.1.9 Real Time Clock
The Real Time Clock circuit in the Model 4 provides a
30 Hz (in the 2 MHz CPU Mode) or 60 Hz (in the 4
MHz CPU Mode) interrupt to the CPU. By counting
the number of interrupts that have occured, the CPU
can keep track of the time. The 60 Hz vertical sync
signal from the video circuitry is divided by two (2
MHz Mode) by U53, and the 30 Hz at pin 1 of U51 is
used to generate the interrupts. In the 4 MHz mode,
signal FAST places a logic low at pin 1 of U51,
causing signal VSYNC to trigger the interrupts at the
60 Hz rate. Note that any time interrupts are disabled,
the accuracy of the clock suffers.
3.1.10 Cassette Circuitry
The cassette write circuitry latches the two LSBs (DO
and Dl) for any output to port FE (hex). The outputs
of these latches (U27) are then resistor summed to
provide three discrete voltage levels (500 Baud only).
The firmware toggles the bits to provide an output
signal of the desired frequency at the summing node.
There are two types of cassette Read circuits - 500
baud and 1 500 baud. The 500 baud circuit is
compatible with both Model 1 and III The input signal
is amplified and filtered by Op amps (U43 and U28.
Part of U15 then forms a Zero Crossing Detector, the
output of which sets the latch U40. A read of Port FF
enables buffer U41, which allows the CPU to
determine whether the latch has been set, and
simultaneously resets the latch. The firmware
determines by the timing between settings of the
latch whether a logic one or "zero" was read in from
the tape.
The 1500 baud cassette read circuit is compatible
with the Model III cassette system. The incoming
signal is compared to a threshold by part of U15.
U15's output will then be either high or low and clock
about one-half of U39, depending on whether it is a
rising edge or a falling edge, If interrupts are enabled,
the setting of either latch will generate an interrupt.
As in the 500 baud circuit, the firmware decodes the
interrupts into the appropriate data.
For any cassette read or write operation, the cassette
relay must be closed in order to start the motor of the
cassette deck. A write to port EC hex with bit one set
will set latch U42, which turns on transistor Q4 and
energizes the relay K1. A subsequent write to this
port with bit one clear will clear the latch and de-
energize the relay.
3.1.11 Printer Circuitry
The printer status lines are read by the CPU by
enabling buffer U67. This buffer will be enabled for
any input from port F8 or F9, or any memory read
from location 37E8 or 37E9 when in the Model III
mode. For a listing of bit status, refer to the bit map.
After the printer driver software determines that the
printer is ready to receive another character (by
reading the status), the character to be printed is
output to port F8. This latches the character into U66,
and simultaneously fires the one-shot U65 to provide
the appropriate strobe to the printer.
3.1.12 I/O Connectors
Two 20-pin single inline connectors, J7 and J8, are
provided for the connection of a Floppy Disk
Controller and an RS-232 Communications Interface,
respectively. All eight data lines and the two least
significant address lines are routed to these
connectors. In addition, connections are provided for
device or board selection, interrupt enable, interrupt
status read, interrupt acknowledge, RESET, and the
CPU WAIT signal.
The graphics connector, J10, contains all of the
above interface signals, plus CRTCLK, the dotclock
signal, a graphics enable input, and other timing
clocks which synchronize the graphics board with the
CRTC.
The I/O bus connector, J2, contains connections for
all eight data lines (buffered by U74), the low order
address lines (buffered by U73), and the control lines
(buffered by U75) IN*, OUT*, RESET*, M1*, and
IORQ*. In addition, the I/O bus connector has inputs
to allow the device(s), connected to generate CPU
WAIT states and interrupts. The sound connector,
J11, contains only four connections: sound enable
(any output to port 90 hex), data bit D0, Vcc, and
ground.
3.1.13 Sound Option
The Model 4 sound option, available as standard
equipment on the disk drive versions, is a software
intensive device. Data is sent out to port 90H,
alternately setting and clearing data bit D0. The state
of this bit is latched by sound board U1 and amplified
by sound board Q1, which drives a piezoelectric
sound transducer. The speed of the software loop
determines the frequency, and thus, the pitch of the
resulting tone.
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