3-67
Since the position of the character on the screen is
related directly to the RAM location, the LSBs of the
Display Counter are used to position the character on the
crt screen.The six LSBs of the counter are appliedto the
Horizontal DAC and select 1-of-64 character locations on
Readout State Machine
The ReadoutState Machineproducesthe alphanumeric
readout on the crt from character-codedata stored in the
Horizontal RAM. For readout displays, the face of the crt
is vertically divided into 16 character lines each having 40
horizontal character positions on the line. Each of these
character positions corresponds to a specific location in
the readout memoryspace (stored in the Horizontal RAM).
To display the readout, the Readout State Machine
sequentially reads through the readout memory and
displays the required character at the corresponding
(memory-mapped) location on the crt screen. Each
displayed character consists of a sequence of individual
dots producedby the Readout State Machine.
The HZON (host Z-Axis on) bit applied to U450B from
the Misc Register(U540)allows the System /.LPto turn the
Z-Axis on during diagnostics and allows verification of Z-
Axis functionality. When set LO, HZON produces a LO at
the output of U450B output, and thus at the ZON (Z-Axis
on) output of U223C.This keepsthe Z-Axis turned on until
the HZON bit is reset HI by the processor.
When the other (active) cursoris to be displayed, the
System /.LPsets the ACTIVELC bit HI. The output of
U412A is then dependent on the DC3 signal from the
Display Counter. The DC3 signal has a 50% duty cycle
and changes states every eight characters (for cursors,
the character is a single dot), so the resultant cursor
display appears as a dashedline.
When displaying the inactive cursor (the one not
selected for control by the cursor pot), the ACTIVELC
(activeline cursor) bit from the Misc Register to pin 2 of
U412A is set LO. This causes the output of U412A to be
HI, and the Z-Axis remains on as long as that particular
cursor is beingdisplayed.
For cursor displays, the HI DISPLAY signal enables D
flip-flop U414B, and the 250 kHz clock beginsclocking the
data from the output of U312B to the
Q
output of U414B.
Since a cursor display is neither a waveform nor a readout
display, the DOTS signal applied to inverter U413D is LO
while the RO signal applied to NAND-gate U3128 is HI.
This enables U312B, and the output of U412A then con-
trols the D input signal to flip-flop U414B. That signal is
clocked to the
Q
output and applied to U223C to control
the Z-Axis signalZON.
Theory of Operation-2430 Service
For waveform displays,the DOTS bit from DisplayCon-
trol Register U530 will be set HI by the System /.LP.This
HI, along with the HI DISPLAY signal from the Display
State Machine, enables U312C. As long as a waveform
display is taking place,the 250 kHz clock turns the display
dots on and off with a 50% duty cycle via U312C and
U223C. When the Display State Machinedetermines that
the waveform display is over, it sets its DISPLAY bit LO,
disabling U312C.For nonwaveformdisplays,the DOTS bit
is LO, also disablingU312C.
During readout displays, the RZON(readout Z-Axis on)
signal from the Readout State Machineis LO for each
point that should be turned on and HI when the display
should be blanked. The level of this signal is sampled by
U415B at a 5 MHz rate. The
Q
output of U4158 controls
the Z-Axis through U450B and U223C,and sinceit is syn-
chronized to the 5 MHz clock used to clock the Readout
State Machine,the intensity of each dot is not the same.
To enable readout or waveform displays, the Display
State Machine sets its DISPLAY output HI. This enables
U415B, U414B,and U312C.
Z-Axis Logic
The Z-Axis Logic determines when to turn the display
beam on or off for each of the various display modes.
These displays are readout, waveform, cursor-normal,
cursor-dashed,and diagnostic(host-forced)Z-Axis on.
The STOPDIS bit applied to the reset inputs of U414A
and U415A provides the System /.LPwith a way to stop
any display in process.
Displaying a single waveform requires 512 data points
be read from RAM, so STOP512 is set HI. A two-
waveform display or a single-waveform envelope display
will require STOP1024 to be HI. Readout displays may
also consist of up to 16 lines of readout, in which case
STOP1024 would be set. This is further explained in the
Readout State Machine description.
The DISDN signal is also sent to the System /.LPInter-
rupt Logic to tell it when the currently assigned display
task is complete. When the processor detects the HI
DISDN, it writes data out to the display register to start
the next display cycle. The System /.LP,knowing how much
waveform and readout data needs to be displayed, does
the writing at a rate that keeps the overall display-refresh
rate constant.
To Next Page
Loading...
Need help?
General
