The two display-controlbits, STOP512and STOP1024,
applied to U313 determine how many data bytes are read
from the selected display RAM (Horizontal, Vertical, and
Attribute) before stopping the current display cycle. Only
one of these two bits is HI at any time. The outputs of the
unselectedAND gates within U313 are LO, and along with
the LO caused by the LO STARTDIS bit, enable the out-
put gate of U313. The selected AND gate watches its
appropriate counter bit and, on the falling edge of the bit,
causes a clock at the output of U313.This clocks the now
LO STARTDIS bit to the
Q
output of U414A, disabling
U411C (and thus clocks to the Display Counter), and
resets the DISDNat the
Q
output HI in preparationfor the
next displaycycle.
If waveform data is to
be
displayed,RO from the Mode
Control Register is HI and RO is LO. The LO RO level
applied to U412C closes the CLKRAM path (output of
U412C is held HI) while the HI RO level applied to U412D
opens the 250 kHz clock path through U412D and U411C.
With the DISPLAY bit to U411C set HI, clocks from
either U412C or U412D clock the Display Counter. Which
one does the clocking dependson whether the data to be
displayed is readout or waveforminformation. If readout
information is being displayed,the RO bit (from the Mode
Control Register) applied to U412D will be LO, disabling
the 250 kHz clock (output of U412D is held HI). At the
same time,
RIO
applied to U412Cis HI, enabling the
CLKRAM (clock RAM) signal from the Readout State
Machineto clock the addresscounters.
The DISPLAY bit is delayed slightly by the propagation
delays of the START bit through the flip-flops and gates.
Therefore, the PRESTART bit is written HI to cause the
output of U323A to be HI until the DISPLAY bit is latched
into flip-flop U414A. The HI PRESTART
+
DISPLAY bit
from U323A selects the counter outputs to address the
Display RAMs (via the Address Multiplexer stage). After
the DISPLAY bit is latched into U414A, the System ILP
sets the START and PRESTART bits from the Display
Control Register LO. The LO START bit is clocked to the
Q
output of U415A,disabling the 250 kHz clocks through
U313 to U414A, and the LO PRESTART bit allows the
DISPLAY signalto control OR-gate U323A.
three lower AND gates within U313 are LO, thereby ena-
bling the output AND gate (it has inverting inputs). With
the previous display cycle finished (as it is for this discus-
sion), the DISDN (display done) bit applied to pin 10 of
U313 is also HI. The 250 kHz clock appliedto this enabled
AND gate causes the output of U313 to go HI on the fai-
ling edge to clock the HI STARTDIS bit to the
Q
output of
U414A. This latched signal is the DISPLAY bit that
enablesthe DisplayCounterclocks (via U411C).
3-66
To start a display, the System ILPwrites a HI for the
START bit into Display Control Register U530. This HI is
appliedto the D input of flip-flop U415A and clocked to its
Q
output on the falling edge of the 250 kHz clock (rising
edge of the 250 kHz clock). This latched STARTDIS bit
(HI)is then appliedto the D input of U414A and to pin 9 of
U313. Since the Display Counter has not reachedits final
value (this is the starting point), the output level of the
Display State Machine
The Display State Machinedetermineswhen display of
stored data should start and stop, depending on other
conditions in the DisplaySystem.
Exclusive-ORgate U350S is used to invert counter bit
DCO when displaying envelope data (ENV is HI). This
causes data pairs (max-min) to be read outin reverse
(relative to how they were stored) and produces an
envelopedisplaythat always starts with a MIN point.
When the Waveform ILP is writing acquired data into
the display RAMs (Horizontal or Vertical), the Display
State Machine selects the WaveformilP address bus
(WAO-WAS)as the source for RAM addresses by setting
the COUNTSEL(counter select) line LO. When displaying
the stored data, COUNTSELis HI, and the outputs from
the Display Counter are routed to the various RAM
addresslines.
Address Multiplexer
The Address Multiplexer stage, under control of the
Display State Machine,selects the addresssource for the
various display RAMs from either the Waveform ILP
addressbus or the DisplayCounter.
The outputs of the counters change synchronouslyand
are applied to the Multiplexer stage, which selects
between these counter outputs and the microprocessor
address bus for Display RAM addresses.The MAX output
from U222 (occurringon count 15) is used in the Readout
State Machine.
enables U220. Due to a two-gate propagation delay
through U222 to the RCO output, U220 will still
be
enabled on the rising edge of the next clock. This clocks
U220,which is then disableduntil U222 counts another 16
clocks. Counting continues, and eventually the RCO out-
put of U220 enables U211, causing it to increment in a
similar fashion. Counting continues until the Display State
Machine determines that the desired display is complete,
at which time it shuts off clocks to the counter.
Theory of Operation-2430 Service
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