3-65
To display stored data, the System J-lPwrites the eight
MSBs of the 12-bit starting RAM address into U211 and
U220 over the data bus by generating a LO LDCOUNT
from the Register Select stage. The 4 LSBs of the address
(all LO) are also loaded at the same time into U222. The
counter then starts counting at the selected rate. When
the count in U222 reaches lS, its RCO (ripple-carry out-
put) goes LO for the last half of the clock cycle and
Display Counter
The Display Counter stage, made up of U211, U220,
and U222, generates the sequential addressing that the
Display and Readout State Machines use to read the
stored waveform and character data out of the display
RAM. Depending on the type of information to be read
from RAM (waveform or readout), clocks to the counter
are selected by logic to produce waveform and readout
displays at the proper refresh rates.
For waveform displays, RO applied to U412C is LO,
holding its output to U411CHI. This HI, along with the HI
DISPLAY bit, enables U411C, and the output of U411C
follows the 2S0 kHz signal applied to U412D (Since RO is
HI). For readout displays, RO and
RO
are HI and LO
respectively. This holds the output of U412D HI, and the
output of U411C follows the CLKRAM (clock RAM) signal
from the Readout State Machine. To completely disable
the Counter clocks, the Display State Machine sets the
DISPLAY bit applied to U411C LO.
Gates U411C, U412C, and U412D make up a clock-
steering circuit that selects the source for clocks to the
counters, depending on display mode. When displaying
waveforms, readout, or cursors, the DISPLAY bit applied
to U411C is HI. The RO and
RO
signals, applied to U412C
and U412D respectively, do clock selection depending on
whether readout or waveform data is to be displayed.
Buffer U413A inverts the 2S0 kHz clock used for the Z-
Axis and Display State Machines.
The S MHz clock is also applied to the counter made
up of decade counters U410A and U410B, producing
several intermediate clocks at their outputs. The 1 MHz
2QC clock, the SOOkHz 2QA clock, and the 2S0 kHz clock
from U410B are gated together by U411A and produce
the SAMPLE clock, having a LO duty cycle of 12.S%.
The S MHz clock signal from the Time Base Controller
circuit is buffered and inverted by U413C and is used to
drive the Readout State Machine.
Theory of Operation-2430 Service
Display Clocks
The state machines of the Display System run on
clocks derived from the S MHz clock of the Secondary
Clock Generator U710 (diagram 7). The Display Clocks cir-
cuit provides the signal frequency division and gating logic
to properly condition clocks for the Display System cir-
cuitry.
Buffer U540 allows the System J-lPto read back the
contents of the Miscellaneous Register.
Miscellaneous Register
Operation of the Miscellaneous Register is identical to
that of the Display Control Register just described. The
output bits control miscellaneous circuit functions, as the
register name implies. The function of each bit is explained
in the description of the associated circuitry.
The buffer U531 provides a way for the System J-lPto
read back the contents of the Display Control Register.
Display Control Register
The operation of Display Control Register U530 is simi-
lar to that just described for the Mode Control Register.
When enabled (by DISCON), data from the data bus is
written into U530 on the rising edge of the System J-lPWR
(write) clock. These data bits determine how many data
paints are displayed, whether the display is to be read
from memory in envelope mode (ENV), and whether the
intensity of each dot should be bright or dim (DOTS).
Buffer U542 provides a way for the System J-lPto read
back the data written to the Mode Control Register US41.
NAND gates U340C and U340D do not allow the YON
and XON enables (controlling the vertical and horizontal
RAMs respectively) unless the display counter is running
(PRESTART + DISPLAY is HI). Exclusive-OR gate U3S0C
and tristate buffer U423B are used to enable horizontal-
deflection bit DXl only when the time cursor is being
displayed (both RO and COUNTEN are LO). The remain-
ing bits from the mode-control register are NANDed with
the DISP (display running) signal and only affect their
associated functions while the Display State Machine is
running.
latched bits are used as enables to other portions of the
display circuitry and control the overall function of the
display.
To Next Page
Loading...
Need help?
General
