The concept of adding the programmable functionality of the NPU within a switching ASIC was originally
designed and implemented in the popular HP ProCurve Switch 4000M family introduced in 1998. The
programmable capability of the HP ProCurve Switch 5300xl was a second-generation design based on the
original HP ProCurve Switch 4000M implementation. The programmable capability was used to give both the
HP ProCurve Switch 4000M and Switch 5300xl new ASIC-related features well after initial release of those
products. The customers’ investments in the HP ProCurve Switch 4000M and 5300xl are preserved by new
functionality not otherwise possible without the ASIC NPU programmability.
Being based on the HP ProCurve Switch 4000M and 5300xl implementations, the NPU capabilities of the
ProVision ASICs used in the HP ProCurve Switch 3500, 5400zl, 6200yl, and 8200zl series are a third-
generation design.
Fabric Interface
After the packet header leaves the programmable section, the header is forwarded to the Fabric Interface. The
Fabric Interface makes final adjustments to the header, based on priority information, multicast grouping, etc.,
and then uses this header to modify the actual packet header as necessary.
The Fabric Interface then negotiates with the destination ProVision ASICs for outbound packet buffer space. If
congestion is present on the outbound port, WRED (weighted random early detection) can be applied at this
point as a congestion-avoidance mechanism. Finally, the ProVision ASICs’ Fabric Interface forwards the entire
packet through the Fabric-ASIC to an awaiting output buffer on the ProVision ASICs that controls the outbound
port for the packet. Packet transfer from the ProVision ASICs to the Fabric-ASIC is accomplished using the 28.8
Gbps full-duplex backplane connection, also managed by the Fabric Interface.
ProVision ASIC CPU
Each ProVision ASIC contain its own CPU for learning of Layer 2 nodes, packet sampling for the XRMON
function, handling local MIB counters, and running other module-related operations. Overall, the local CPU
offloads the master CPU by providing a distributed approach to general housekeeping tasks associated with
every packet. MIB variables, which need to be updated with each packet, can be done locally. The Layer 2
forwarding table is kept fresh through the use of this CPU. Other per-port protocols, such as Spanning Tree
and LACP, are also run on this CPU. The local CPU, being a full-function microprocessor, allows functionality
updates through future software releases.
Fabric ASIC
The Fabric ASIC, which is located on the backplane of the switch, provides the crossbar fabric for
interconnecting the modules together. The use of a crossbar allows wire-speed connections simultaneously from
any module to any other module. As mentioned in the ProVision ASICs section, the connection between the
Fabric-ASIC and each line interface module’s ProVision ASIC is through a 28.8 Gbps full-duplex link.
Management subsystem
The management subsystem is responsible for overall switch management. The management subsystem
consists of a CPU, flash memory to hold program code, processor memory for code execution, status LEDs and
pushbuttons, a console interface, and other system support circuitry to interface and control each line interface
module. In the case of the Switch 5400zl series, the management subsystem is on a module that is removable/
upgradable. Each 5400zl series chassis requires one management module to function. For the HP ProCurve
Switch 3500 and 6200yl series, the management subsystem is an integrated component. The Switch 8200zl
series offers a modular management subsystem and can also be deployed with redundant management
modules for enhanced system availability.
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