4 - 5
4-3-4 VCO CIRCUIT (MAIN UNIT)
• TX-VCO/CHANNEL 70-VCO (RX) CIRCUITS
The VCO outputs from TX-VCO/CHANNEL 70-VCO (Q18)
are amplified at the buffer amplifiers (Q19 and Q27), and are
applied to the TX/RX switch circuit (D42, D43). The receiver
LO signal is applied to the 1st mixer circuit for CHANNEL 70
(D21, L48, L49) passing through a low-pass filter (L51, L52,
C150–C152), and the transmitter signal is applied to the pre-
drive amplifier (Q28). A portion of the VCO output signal is
re-applied to the PLL IC (IC2, pin 2) via the buffer amplifier
(Q15).
• OTHER CHANNELS-VCO (RX) CIRCUITS
The VCO outputs from OTHER CHANNELS-VCO (Q12) are
amplified at the buffer amplifiers (Q13 and Q23). The receiv-
er LO signal is applied to the 1st mixer circuit for OTHER
CHANNELS (D11, L18, L19) passing through a low-pass fil-
ter (L21, L22, C52–C54). A portion of the VCO output signal
is re-applied to the PLL IC (IC2, pin 2 or pin 19) via the buffer
amplifier (Q19).
4-4 DSC CIRCUITS
4-4-1 DSC MODULATION CIRCUIT
(LOGIC, AF AND MAIN UNITS)
The ATIS signal from the CPU (LOGIC unit; IC1, pin 117) is
applied to the buffer amplifier (AF unit; Q18) as “DSC” sig-
nal. The signal passes through the analog switch (AF unit;
IC7, pin 1), and then applied to IDC amplifier (AF unit; IC8a).
Then, the amplified signal is applied to the transmitter cir-
cuit.
The signalis passed through the splatter filter (AF unit; IC8b)
to suppress unwanted 3 kHz or higher signals. The filtered
signals are then applied to the TX modulation circuit via the
D/A converter IC (MAIN unit; IC15, pins 11, 12) as a DSC
modulation signal “MOD”.
4-5 LOGIC CIRCUITS
4-5-1 MAIN UNIT
• CPU
IC1 is a 8 bit single chip micro-computer, which contains
LCD driver, serial I/O, timer, A/D converter, programmable
I/O, ROM and RAM.
• SYSTEM CLOCK CIRCUIT
X1 is a crystal oscillator, which oscillates 9.8304 MHz sys-
tem clock for the main CPU (IC1).
• RESET CIRCUIT
IC2 is a reset IC, which outputs a reset signal (“LOW” pulse)
to main CPU (IC1, pin 79) when turning transceiver power
ON.