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2.8.2.1 LVDS Interface
The LVDS flat panel display interface supports the following:
1366 x 768 @ 60 Hz resolution
Single-channel and dual-channel interface, up to 135 MHz clock rate 18 bpp and
24 bpp (VESA* and JEIDA mappings) color depth support
Multiple EDID data source capability (panel, predefined, and custom payloads)
3.3 V, 5 V, and 12 V flat panel display voltage flexibility, with up to 3 A current
5V, 12 V and Vin backlight inverter voltage flexibility, with up to 3 A current
Backlight inverter signal redundancy on dedicated header as well as on LVDS
connector (for discrete inverter or panel-integrated inverter support using a single
cable)
Flat panel brightness control via front panel button input as well as Windows* 7
brightness adjustment slider
Spread-spectrum control
NOTE
Bac
board power input connector.
NOTE
Support for flat panel display configuration complies with the following:
1. Internal flat panel display settings are not exposed through Intel
®
Integrator
Toolkit or Intel
®
Integrator Assistant GUIs.
2. Internal flat panel display settings will not be overwritten by loading BIOS setup
defaults.
3. Internal flat panel display settings will be preserved across BIOS updates.
2.8.2.2 Embedded DisplayPort (eDP) Interface
The eDP (Embedded DisplayPort) flat panel display interface supports the following:
1366 x 768 @ 60 Hz resolution
1-lane, 2-lane, and 4-lane bandwidth at 1.62 Gb/s or 2.7 Gb/s
Multiple EDID data source capability (panel, predefined, and custom payloads)
3.3 V, 5 V, and 12 V flat panel display voltage flexibility, with up to 3 A current
5V, 12 V and Vin backlight inverter voltage flexibility, with up to 3 A current
Backlight inverter signal redundancy on a dedicated header as well as on eDP
connector (for discrete inverter or panel-integrated inverter support using a single
cable)
Flat panel brightness control via front panel button input as well as Windows 7
brightness adjustment slider
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