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BIOS Setup
Advanced Chipset Features
MSI Reminds You...
Change these settings only if you are familiar with the chipset.
DRAM Timing Selectable
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to By SPD enables DRAM
timings to be determined by BIOS based on the configurations on the SPD.
Selecting Manual allows users to configure the DRAM timings manually.
CAS Latency Time
This controls the timing delay (in clock cycles) before SDRAM starts a read
command after receiving it. Settings: 2, 2.5, 3 (clocks). 2 (clocks) in-
creases the system performance the most while 3 (clocks) provides the most
stable performance.
Active to Precharge Delay
The field specifies the idle cycles before precharging an idle bank.
Settings: 8, 7, 6, 5 (clocks).
DRAM RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay between
the CAS and RAS strobe signals, used when DRAM is written to, read from
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