NI Digital System Development Board User Manual | © National Instruments | 19
DDR3 Memory
The DSDB includes two Micron MT41J128M16JT-125 or MT41K128M16JT-125 DDR3
memory components creating a single rank, 32-bit wide interface and a total of 512MiB of
capacity. The DDR3 is connected to the hard memory controller in the Processor Subsystem
(PS), as outlined in the Xilinx Zynq TRM (ug585).
The PS incorporates an AXI memory port interface, a DDR3 controller, the associated PHY, and
a dedicated I/O bank. Interface speeds of up to 525MHz/1050 Mbps are supported.
DDR3 uses 1.5 V SSTL15 single-ended and DIFF_SSTL15 differential signaling. Address and
control signals are routed in a tree topology with minimal stubs and series termination scheme.
Data signals follow a point-to-point scheme and benefit from on-die termination (ODT) on both
ends.
The target trace impedance is 40 (±10%) for single-ended signals, and 80 (±10%) for
differential. A feature called DCI (Digitally Controlled Impedance) is used to match the drive
strength and termination impedance of the PS pins to the trace impedance. On the memory side,
each chip calibrates its on-die termination and drive strength using a 240 resistor on the ZQ
pin.
Due to layout reasons, the two lower data byte groups (DQ[0-7], DQ[8-15]) were swapped. To
the same effect, the data bits inside byte groups were swapped as well. These changes are
transparent to the user. Appropriate Xilinx PCB guidelines were followed during design.
Both the memory chips and the PS DDR bank are powered from the 1.5 V supply. The mid-point
reference of 0.75 V is created with a simple resistor divider and is available to the Zynq as
external reference.
For proper operation it is essential that the PS memory controller is configured properly. Settings
range from memory timings to the board trace delays. For your convenience, the Zynq preset file
for the DSDB is provided on the Digilent DSDB Resource Center and can be used to
automatically configure the correct parameters.
For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read
data eye options in the PS Configuration Tool in Xilinx tools. Training is done dynamically by
the controller to account for board delays, process variations, and thermal drift. Optimum
starting values for the training process are the board delays (propagation delays) for certain
memory signals. process variations, and thermal drift. Optimum starting values for the training
process are the board delays (propagation delays) for certain memory signals.
Board delays are specified for each of the data byte groups in absolute terms and then relative to
CLK. These parameters are board-specific and were calculated from the PCB trace length
reports.
For more details on memory controller operation, refer to the Xilinx Zynq TRM (ug585).
To Next Page
Loading...
Need help?
General