NI Digital System Development Board User Manual | © National Instruments | 9
The supply rails are daisy-chained to follow the Xilinx-recommended start-up sequence.
Flicking the power switch (SW9) will enable the 5.125 V (IC53) rail, which enables the 1 V
digital supply rail, which in turn enables the supply rails 1.8 V, 3.3 V, and 1.5 V. The 1.25 V
reference, 1.8 V analog supply and 10V, -5V charge pumps ramp together with the 3.3 V rail.
Once all the channels of the ADP5052 (IC55) supply reach regulation, the PGOOD signal will
assert, enabling the 3.3 V audio supply, lighting up the power LED (LD14), enabling user
supplies (IC46, IC49) and power supply for user IO buffers (IC19) and de-asserting the
Power-On Reset signal (PS_POR_B) of the Zynq.
Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an
additional delay of at least 130ms after the power rails reach regulation and before the Power-On
Reset signal de-assert to allow for the PS_CLK (IC22) to stabilize.
Input Power Monitoring
The DSDB includes a TPS25940i power monitoring switch placed on the 5 V input power rail.
This circuit provides input over and under voltage protection, fast response short-circuit
protection, and slew rate controlled startup to limit inrush current. In case the input supply
voltage is outside the operating range of 4.6 V to 5.5 V, or if the current consumption exceeds
4.4 A, the TPS25940 will turn off the board power.
User Power Supplies
The DSDB provides two user power supplies, 5 V and 3.3 V. The 5 V user supply is available
at the MXP connector, while the 3.3 V is accessible at the PMODs (JA, JB, JC), MXP connector
(J4) and in the digital breadboard (BB3). Each of these two power supplies are able to source up
to 0.3 A and provide the following protection features:
• Short-circuit protection
• 0.3 A current limitation
• Reverse current protection
• Zener protection from accidental shorts to a higher voltage
• Protection from accidental shorts to a reverse polarity voltage
Both of these user supplies turn on automatically after the 5.125 V and FPGA supplies (3.3 V,
1 V, 1.8 V, 1.5 V) are in regulation and the PGOOD signal is asserted. As soon as the PGOOD
signal is deactivated, these user supplies turn off. Alternatively, the user has the ability to disable
these outputs from the FPGA by driving the USER_POWER_EN signal low.
Besides disabling user supplies the USER_POWER_EN signal will also deactivate, the 4.28 V
voltage, which is powering the buffers on the digital IOs that go to PMODs (JA, JB, JC), MXP
(J4) and digital breadboard. This way, the communication between FPGA and the above
mentioned expansion connectors is interrupted.
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