Reference
Bottom Side Description
State Input Source Sets the state signal source.
Logic
Sets the signal log ic for state input source.
H = high true, L = low true.
Clock Input Source Sets th e clock signal source.
Define
Inputs
Slope Sets the signal slope (rising or falling) for clock
input. The clock slope defines when the clock
signal is true.
Goes True Triggers th e osci
lloscope if the state signal is
true when the clo
ck signal slope is true.
Trigger
When
Goes False Triggers th e oscilloscope if the state signal is
false when the clock signal slope is true.
Level (State
Input)N
Level (Clock Input )
N
Sets the threshold voltage level for state and
clock signals to level N, using the general
purpose knob.
Set to TTL Sets the threshold voltage level to 1.4 V for
both input s.
Set to ECL Sets the threshold voltage level to -1.3 V for
both input s.
Thresholds
Set to 50% Sets the threshold vo ltage level to 50% of each
input's peak-to-peak value.
Mode &
Holdoff
The table on Edge triggering includes a
description of this menu item. (See page 114.)
Key Points
Trigger When. The state signal must be true or false for ≥2nspriorto
the c lock transition in order for the oscilloscope to detect the state.
Pulse Triggers
Pulse Width Trigger. Pulse-width triggering triggers the oscilloscope
when a signal pulse width is less than, greater than, equal to, or not
equal to a specified pulse width. Th is trigger is u seful for digital logic
troubleshooting.
TDS3000C Series O scilloscope User Manual 123
To Next Page
Loading...
Need help?
General
