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Cisco ASR 1000 Series Aggregation Services Routers Hardware Installation Guide
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Chapter 3 Cisco ASR 1000 Series Routers Embedded Services Processors
Cisco ASR 1000-ESP200
The following figure displays an example of a packet flow in the Cisco ASR 1000 ESP 200.
Figure 3-2 Packet flow in the Cisco ASR 1000 ESP 200
Implications of SIP and SPA Slot Mapping
Interfaces and sessions that have an egress QoS have their schedules and queues present in the
QFP-3rd-Gen ASIC that services the particular slot. Since there is a limitation of 29000 schedules and
116000 queues per QFP-3rd-Gen ASIC, multiple QFP-3rd-Gen ASICs should be targeted by placing the
SIP and SPA in the correct order, in order to achieve full system scalability for schedules and queues.
For example, A 5xGE SPA supports more than 32000 point-to-point protocol (PPP) sessions depending
on the ESP. However, if QoS is applied to these sessions, the QFP-3rd-Gen ASIC that supports the SIP
and SPA slot can support only 29000 schedules, and these sessions share the 116000 queue limit. To
support PPP sessions with QoS that are greater than 29000, a different SIP and SPA should be used to
map to a different QFP-3rd-Gen ASIC. This will enable additional schedules and queues.
1 Egress queueing for interfaces handled by
QFP-3rd-Gen 3
3 Egress queueing for interfaces handled by
QFP-3rd-Gen 1
2 Egress queueing for interfaces handled by
QFP-3rd-Gen 2
4 Egress queueing for interfaces handled by
QFP-3rd-Gen 0
PPE1
PPE1
PPE1
PPE1
PPE1
PPE1
PPE1
PPE2
PPE1
PPE1
PPE1
PPE3
PPE1
PPE1
PPE1
PPE4
PPE1
PPE1
PPE1
PPE5
PPE1
PPE1
PPE1
PPE6
PPE1
PPE1
PPE1
PPE40.....
Processor pool
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
QFP
Dispatcher/
Pkt Buffer
PPE1
PPE1
PPE1
PPE1
PPE1
PPE1
PPE1
PPE2
PPE1
PPE1
PPE1
PPE3
PPE1
PPE1
PPE1
PPE4
PPE1
PPE1
PPE1
PPE5
PPE1
PPE1
PPE1
PPE6
PPE1
PPE1
PPE1
PPE40.....
Processor pool
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
QFP
Dispatcher/
Pkt Buffer
PPE1
PPE1
PPE1
PPE1
PPE1
PPE1
PPE1
PPE2
PPE1
PPE1
PPE1
PPE3
PPE1
PPE1
PPE1
PPE4
PPE1
PPE1
PPE1
PPE5
PPE1
PPE1
PPE1
PPE6
PPE1
PPE1
PPE1
PPE40.....
Processor pool
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
QFP
Dispatcher/
Pkt Buffer
PPE1
PPE1
PPE1
PPE1
PPE1
PPE1
PPE1
PPE2
PPE1
PPE1
PPE1
PPE3
PPE1
PPE1
PPE1
PPE4
PPE1
PPE1
PPE1
PPE5
PPE1
PPE1
PPE1
PPE6
PPE1
PPE1
PPE1
PPE40.....
Processor pool
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
QFP
Dispatcher/
Pkt Buffer
QFP0 QFP1 QFP2 QFP3
Interconnect
SIP0 SIP1 SIP2 SIP3 SIP4 SIP5
36
1393
Interconn.
IOCP
SPA SPA SPA SPA
SPA
Agg.
Interconn.
IOCP
SPA SPA SPA SPA
SPA
Agg.
Interconn.
IOCP
SPA SPA SPA SPA
SPA
Agg.
Interconn.
IOCP
SPA SPA SPA SPA
SPA
Agg.
Interconn.
IOCP
SPA SPA SPA SPA
SPA
Agg.
Interconn.
IOCP
SPA SPA SPA SPA
SPA
Agg.