HP 8340b Operating Instructions

This applies also to internal leveling. When externally leveled with a linear detector the relationship is:
Vout = Vo X (Vin +1)2
A power meter is a square law detector, so AM with power meter leveling is linear. For bandwidth see
the external leveling secton.
For simultaneous AM and pulse modulation, see the next section.
PULSE MODULATION
The HP 8340B/41B provides leveled pulse modulation over a wide range of pulse widths and rates.
Characteristics such as leveling accuracy and response time vary with pulse width, pulse rate, tem¬
perature, power level, and RF frequency. In order to use the pulse leveling system to best advantage it
is helpful to understand its operation and limitations.
Sample and Hold Leveling
The basic leveling loop was previously explained with reference to Figure 3-29. Fundamental to its
operation is the internal detector which measures the RF amplitude. The leveling performance is
limited by the accuracy of this measurement. The most difficult aspect of leveled pulse modulation is
measuring the amplitude of a very narrow RF pulse.
Figure 3-34 is a block diagram of the detector circuitry, with waveforms. Trace 1 is the pulse modula¬
tion input signal to the HP 8340B/41B. It controls a fast RF modulator which is either full on or full off.
The amplitude when on is controlled by the linear modulator used for CW leveling and AM. Trace 2 is
the resultant RF pulse, which is the HP 8340B/41B’s output. This pulse is detected by the crystal
detector. It trails the pulse input by 55 nsec, representing propogation delays in the pulse modulator
and its drive circuits.
The output of the crystal detector is amplified by a logarithmic amplifier (log amp). The log amp is used
for several reasons, one of which is its high gain for small signals, reducing the effects of sample and
hold errors. Trace 3 is the output of the log amp. The delay and relatively slow rise time are caused by
the finite bandwidths of the detector and log amp. The pedestal (arrow) represents the RF amplitude.
This level is captured for further processing by the sample and hold circuit (S/H), represented by the
switch-capacitor combination. Trace 4 shows the signal controlling the switch, which is closed when
trace 4 is high.
Trace 4 is timed to coincide with the pedestal of trace 3. This timing is done by circuitry associated
with the pulse modulator and is factory adjusted for best coincidence. Since the S/H switch is closed
only during trace 3’s pedestal, the capacitor charges to a constant dc voltage. This voltage is the same
as what comes out of the log amp during CW operation at the same power level. The capacitor is
isolated by a buffer to prevent the following circuits from discharging it between pulses. The output of
the buffer is compared to the ALC inputs in the same manner as with CW operation.
Figure 3-34 shows a 200 nsec pulse. If the pulse were narrowed to 100 nsec, trace 3 would not quite
reach its pedestal before it begins to fall. The result is a dc output from the S/H that is smaller than it
would be in CW. The ALC circuits respond by raising the RF output until that voltage is what it should
be. This is the reason for poor leveling accuracy with narrow pulses. As the pulses are made nar¬
rower, their amplitude grows.
3-110 Operating Information
HP 8340B/41B

HP 8340b Specifications

General

Brand	HP
Model	8340b
Category	Inverter
Language	English